Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67976944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13572689

1

T1

13

T2

18

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80347362	1			T1	1479		T2	22		T3	17564
values[0x0]	583359	1			T1	5		T2	8		T3	27
values[0x1]	618912	1			T1	8		T2	8		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46816355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34733278

1

T1

505

T2

19

T3

8889

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	298131	1			T1	6		T3	92		T11	4
valid_sources[0x01]	313953	1			T1	6		T3	68		T12	34
valid_sources[0x02]	307154	1			T1	4		T3	69		T11	4
valid_sources[0x03]	277818	1			T1	6		T3	61		T11	3
valid_sources[0x04]	283673	1			T1	3		T3	59		T11	4
valid_sources[0x05]	308451	1			T1	7		T2	1		T3	83
valid_sources[0x06]	300005	1			T1	6		T3	81		T11	2
valid_sources[0x07]	344477	1			T1	3		T3	68		T12	36
valid_sources[0x08]	315073	1			T1	8		T3	76		T11	3
valid_sources[0x09]	299297	1			T1	7		T3	69		T12	21
valid_sources[0x0a]	369916	1			T1	2		T3	64		T12	45
valid_sources[0x0b]	325388	1			T1	6		T3	55		T5	1
valid_sources[0x0c]	327929	1			T1	7		T3	86		T11	1
valid_sources[0x0d]	282581	1			T1	5		T3	62		T11	3
valid_sources[0x0e]	299178	1			T1	7		T3	73		T12	36
valid_sources[0x0f]	298619	1			T1	3		T3	82		T5	1
valid_sources[0x10]	289136	1			T1	1		T3	58		T12	40
valid_sources[0x11]	369685	1			T1	7		T3	83		T11	1
valid_sources[0x12]	318553	1			T1	4		T3	75		T12	41
valid_sources[0x13]	387684	1			T1	6		T3	84		T11	7
valid_sources[0x14]	301640	1			T1	4		T3	69		T12	33
valid_sources[0x15]	303617	1			T1	3		T3	80		T11	2
valid_sources[0x16]	296261	1			T1	6		T3	76		T11	1
valid_sources[0x17]	373244	1			T1	5		T3	77		T12	47
valid_sources[0x18]	326533	1			T1	5		T3	61		T12	42
valid_sources[0x19]	319466	1			T1	4		T2	1		T3	66
valid_sources[0x1a]	338374	1			T1	5		T3	65		T12	22
valid_sources[0x1b]	309486	1			T1	6		T3	52		T11	1
valid_sources[0x1c]	300391	1			T1	8		T3	74		T12	50
valid_sources[0x1d]	280904	1			T1	8		T2	3		T3	64
valid_sources[0x1e]	407287	1			T1	6		T3	77		T5	1
valid_sources[0x1f]	338092	1			T1	3		T3	57		T11	1
valid_sources[0x20]	288976	1			T1	6		T3	67		T11	5
valid_sources[0x21]	290929	1			T1	6		T3	75		T5	2
valid_sources[0x22]	322350	1			T1	6		T3	76		T11	2
valid_sources[0x23]	396536	1			T1	7		T3	69		T11	3
valid_sources[0x24]	284729	1			T1	7		T3	72		T11	3
valid_sources[0x25]	283770	1			T1	2		T3	73		T12	46
valid_sources[0x26]	284752	1			T1	2		T2	1		T3	78
valid_sources[0x27]	306794	1			T1	9		T3	64		T4	1103
valid_sources[0x28]	321916	1			T1	7		T3	72		T12	26
valid_sources[0x29]	299676	1			T1	7		T3	56		T11	1
valid_sources[0x2a]	308707	1			T1	9		T3	69		T5	1
valid_sources[0x2b]	334366	1			T1	8		T3	69		T11	1
valid_sources[0x2c]	306563	1			T1	4		T3	59		T11	7
valid_sources[0x2d]	306061	1			T1	10		T3	63		T11	5
valid_sources[0x2e]	288129	1			T1	6		T3	84		T11	1
valid_sources[0x2f]	283089	1			T1	11		T3	57		T12	41
valid_sources[0x30]	302300	1			T1	5		T3	62		T11	3
valid_sources[0x31]	283698	1			T1	5		T3	53		T12	34
valid_sources[0x32]	287600	1			T1	3		T3	75		T11	2
valid_sources[0x33]	351942	1			T1	5		T3	59		T12	39
valid_sources[0x34]	305632	1			T1	2		T3	69		T12	37
valid_sources[0x35]	280381	1			T1	4		T3	66		T11	3
valid_sources[0x36]	303249	1			T1	8		T3	42		T11	2
valid_sources[0x37]	283249	1			T1	2		T3	60		T11	2
valid_sources[0x38]	293899	1			T1	5		T3	82		T12	39
valid_sources[0x39]	307542	1			T1	1		T3	68		T11	1
valid_sources[0x3a]	348212	1			T1	7		T2	2		T3	68
valid_sources[0x3b]	330153	1			T1	2		T3	66		T11	1
valid_sources[0x3c]	308205	1			T1	10		T3	69		T11	1
valid_sources[0x3d]	639569	1			T1	6		T3	72		T12	42
valid_sources[0x3e]	481031	1			T1	6		T3	61		T5	1
valid_sources[0x3f]	307879	1			T1	7		T3	61		T11	2
valid_sources[0x40]	339110	1			T1	10		T2	4		T3	61
valid_sources[0x41]	281393	1			T1	12		T3	56		T11	5
valid_sources[0x42]	316962	1			T1	6		T3	82		T11	1
valid_sources[0x43]	396207	1			T1	8		T3	70		T12	34
valid_sources[0x44]	314644	1			T1	7		T3	87		T11	5
valid_sources[0x45]	441576	1			T1	3		T3	72		T12	31
valid_sources[0x46]	281182	1			T1	7		T2	1		T3	69
valid_sources[0x47]	320409	1			T1	7		T3	65		T11	2
valid_sources[0x48]	303347	1			T1	5		T3	60		T11	3
valid_sources[0x49]	291092	1			T1	12		T3	64		T11	9
valid_sources[0x4a]	342433	1			T1	4		T3	72		T11	3
valid_sources[0x4b]	378463	1			T1	2		T3	55		T11	4
valid_sources[0x4c]	278539	1			T1	4		T3	68		T11	9
valid_sources[0x4d]	322205	1			T1	3		T2	1		T3	58
valid_sources[0x4e]	297366	1			T1	7		T3	61		T12	44
valid_sources[0x4f]	385808	1			T1	7		T3	61		T7	4889
valid_sources[0x50]	340473	1			T1	4		T3	72		T12	24
valid_sources[0x51]	290589	1			T1	4		T3	89		T12	22
valid_sources[0x52]	291590	1			T1	4		T3	67		T12	43
valid_sources[0x53]	278403	1			T1	1		T3	81		T11	2
valid_sources[0x54]	319706	1			T1	6		T3	70		T11	3
valid_sources[0x55]	296562	1			T1	8		T3	79		T11	2
valid_sources[0x56]	312781	1			T1	11		T3	86		T11	5
valid_sources[0x57]	332421	1			T1	5		T3	55		T12	28
valid_sources[0x58]	296696	1			T1	3		T3	65		T5	4
valid_sources[0x59]	343284	1			T1	4		T3	65		T12	43
valid_sources[0x5a]	281530	1			T1	7		T2	1		T3	75
valid_sources[0x5b]	308089	1			T1	4		T3	76		T11	5
valid_sources[0x5c]	268620	1			T1	4		T3	73		T11	2
valid_sources[0x5d]	289658	1			T1	8		T3	67		T11	4
valid_sources[0x5e]	303002	1			T1	2		T3	77		T11	1
valid_sources[0x5f]	300935	1			T1	7		T3	69		T11	3
valid_sources[0x60]	299525	1			T1	6		T3	62		T11	3
valid_sources[0x61]	367415	1			T1	7		T3	58		T11	3
valid_sources[0x62]	300064	1			T1	4		T3	64		T11	4
valid_sources[0x63]	288517	1			T1	2		T3	74		T12	40
valid_sources[0x64]	300184	1			T1	6		T3	93		T11	8
valid_sources[0x65]	332153	1			T3	55		T11	5		T12	34
valid_sources[0x66]	305337	1			T1	5		T3	72		T11	1
valid_sources[0x67]	309556	1			T1	10		T3	70		T5	2
valid_sources[0x68]	304599	1			T1	3		T2	3		T3	71
valid_sources[0x69]	281849	1			T1	7		T3	47		T12	30
valid_sources[0x6a]	305365	1			T1	13		T3	75		T11	2
valid_sources[0x6b]	287308	1			T1	11		T3	74		T5	11
valid_sources[0x6c]	282097	1			T1	3		T3	60		T5	1
valid_sources[0x6d]	313966	1			T1	6		T3	62		T11	1
valid_sources[0x6e]	293767	1			T1	6		T3	60		T5	1
valid_sources[0x6f]	316837	1			T1	3		T3	69		T11	9
valid_sources[0x70]	309673	1			T1	15		T3	53		T11	2
valid_sources[0x71]	296837	1			T1	3		T3	57		T12	39
valid_sources[0x72]	289375	1			T1	8		T3	57		T11	1
valid_sources[0x73]	415371	1			T1	6		T3	84		T11	11
valid_sources[0x74]	297073	1			T1	7		T2	1		T3	69
valid_sources[0x75]	283090	1			T1	14		T3	78		T12	35
valid_sources[0x76]	357917	1			T1	6		T2	2		T3	51
valid_sources[0x77]	340771	1			T1	10		T3	73		T11	1
valid_sources[0x78]	377772	1			T1	12		T3	73		T11	5
valid_sources[0x79]	418225	1			T1	6		T3	58		T11	1
valid_sources[0x7a]	314169	1			T1	4		T3	90		T12	36
valid_sources[0x7b]	328964	1			T1	3		T3	72		T12	40
valid_sources[0x7c]	279563	1			T1	11		T3	80		T12	38
valid_sources[0x7d]	303726	1			T1	3		T3	52		T12	35
valid_sources[0x7e]	333727	1			T1	4		T3	101		T12	38
valid_sources[0x7f]	398840	1			T1	3		T3	74		T12	34
valid_sources[0x80]	316585	1			T1	7		T2	1		T3	69

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12814086

1

T1

7

T2

8

T4

32

values[0x0]

all_enables

biggest_size

404317

1

T1

2

T2

3

T3

20

values[0x1]

all_enables

biggest_size

354286

1

T1

4

T2

7

T3

13