Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	977756	0	0
ctrl_rd_A	2147483647	17864	0	0
intr_enable_rd_A	2147483647	17275	0	0
ovrd_rd_A	2147483647	17178	0	0
timeout_ctrl_rd_A	2147483647	16707	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	977756	0	0
T14	287231	0	0	0
T15	785379	0	0	0
T16	356815	13686	0	0
T18	0	5881	0	0
T26	214904	10299	0	0
T30	747	0	0	0
T32	4933	0	0	0
T33	0	3660	0	0
T34	0	10679	0	0
T35	0	17059	0	0
T36	0	17031	0	0
T37	0	6232	0	0
T38	0	26301	0	0
T39	0	15610	0	0
T40	40249	0	0	0
T41	18180	0	0	0
T42	19901	0	0	0
T43	532606	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17864	0	0
T20	611503	0	0	0
T33	156294	474	0	0
T37	0	249	0	0
T77	3507	0	0	0
T80	0	602	0	0
T81	0	206	0	0
T82	0	688	0	0
T83	0	1011	0	0
T84	0	443	0	0
T85	0	161	0	0
T86	0	743	0	0
T87	0	451	0	0
T88	416540	0	0	0
T89	477924	0	0	0
T90	242564	0	0	0
T91	65261	0	0	0
T92	406476	0	0	0
T93	138793	0	0	0
T94	661978	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17275	0	0
T20	611503	0	0	0
T33	156294	430	0	0
T37	0	173	0	0
T77	3507	0	0	0
T80	0	672	0	0
T81	0	210	0	0
T82	0	547	0	0
T83	0	786	0	0
T84	0	410	0	0
T88	416540	0	0	0
T89	477924	0	0	0
T90	242564	0	0	0
T91	65261	0	0	0
T92	406476	0	0	0
T93	138793	0	0	0
T94	661978	0	0	0
T95	0	12	0	0
T96	0	21	0	0
T97	0	14	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17178	0	0
T20	611503	0	0	0
T33	156294	445	0	0
T37	0	289	0	0
T77	3507	0	0	0
T80	0	766	0	0
T81	0	235	0	0
T82	0	663	0	0
T83	0	764	0	0
T84	0	427	0	0
T85	0	181	0	0
T86	0	725	0	0
T87	0	515	0	0
T88	416540	0	0	0
T89	477924	0	0	0
T90	242564	0	0	0
T91	65261	0	0	0
T92	406476	0	0	0
T93	138793	0	0	0
T94	661978	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16707	0	0
T20	611503	0	0	0
T33	156294	465	0	0
T37	0	253	0	0
T77	3507	0	0	0
T80	0	784	0	0
T81	0	207	0	0
T82	0	539	0	0
T83	0	825	0	0
T84	0	456	0	0
T85	0	108	0	0
T86	0	709	0	0
T87	0	460	0	0
T88	416540	0	0	0
T89	477924	0	0	0
T90	242564	0	0	0
T91	65261	0	0	0
T92	406476	0	0	0
T93	138793	0	0	0
T94	661978	0	0	0