Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	74724	1			T1	2		T2	2		T5	2
all_values[1]	74724	1			T1	2		T2	2		T5	2
all_values[2]	74724	1			T1	2		T2	2		T5	2
all_values[3]	74724	1			T1	2		T2	2		T5	2
all_values[4]	74724	1			T1	2		T2	2		T5	2
all_values[5]	74724	1			T1	2		T2	2		T5	2
all_values[6]	74724	1			T1	2		T2	2		T5	2
all_values[7]	74724	1			T1	2		T2	2		T5	2
all_values[8]	74724	1			T1	2		T2	2		T5	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343892

1

T1

18

T2

18

T5

18

auto[1]

328624

1

T6

6

T7

5

T10

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

608902

1

T1

13

T2

13

T5

13

auto[1]

63614

1

T1

5

T2

5

T5

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	21982	1			T10	1		T11	6		T12	1
all_values[0]	auto[0]	auto[1]	16645	1			T1	2		T2	2		T5	2
all_values[0]	auto[1]	auto[0]	22020	1			T13	2		T16	4		T17	2
all_values[0]	auto[1]	auto[1]	14077	1			T6	1		T7	1		T20	1
all_values[1]	auto[0]	auto[0]	39370	1			T1	2		T2	2		T5	2
all_values[1]	auto[0]	auto[1]	1321	1			T13	2		T15	7		T16	11
all_values[1]	auto[1]	auto[0]	32602	1			T12	6		T13	20		T21	1
all_values[1]	auto[1]	auto[1]	1431	1			T13	1		T16	4		T18	9
all_values[2]	auto[0]	auto[0]	35018	1			T1	1		T2	1		T5	1
all_values[2]	auto[0]	auto[1]	2220	1			T1	1		T2	1		T5	1
all_values[2]	auto[1]	auto[0]	35449	1			T6	1		T10	2		T11	5
all_values[2]	auto[1]	auto[1]	2037	1			T10	1		T12	5		T13	3
all_values[3]	auto[0]	auto[0]	37580	1			T1	2		T2	2		T5	2
all_values[3]	auto[0]	auto[1]	225	1			T15	1		T18	2		T26	3
all_values[3]	auto[1]	auto[0]	36666	1			T6	1		T7	1		T10	4
all_values[3]	auto[1]	auto[1]	253	1			T19	1		T23	2		T116	2
all_values[4]	auto[0]	auto[0]	35077	1			T1	2		T2	2		T5	2
all_values[4]	auto[0]	auto[1]	391	1			T13	1		T22	11		T23	8
all_values[4]	auto[1]	auto[0]	38897	1			T10	3		T12	6		T24	1
all_values[4]	auto[1]	auto[1]	359	1			T13	2		T19	6		T22	6
all_values[5]	auto[0]	auto[0]	37889	1			T1	2		T2	2		T5	2
all_values[5]	auto[0]	auto[1]	145	1			T34	1		T39	1		T86	3
all_values[5]	auto[1]	auto[0]	36514	1			T7	1		T10	4		T11	3
all_values[5]	auto[1]	auto[1]	176	1			T13	2		T34	5		T37	2
all_values[6]	auto[0]	auto[0]	38475	1			T1	2		T2	2		T5	2
all_values[6]	auto[0]	auto[1]	127	1			T13	1		T34	1		T39	1
all_values[6]	auto[1]	auto[0]	35935	1			T6	1		T7	1		T10	4
all_values[6]	auto[1]	auto[1]	187	1			T34	2		T37	3		T39	2
all_values[7]	auto[0]	auto[0]	40146	1			T1	2		T2	2		T5	2
all_values[7]	auto[0]	auto[1]	328	1			T23	12		T116	1		T120	3
all_values[7]	auto[1]	auto[0]	33975	1			T6	1		T7	1		T10	1
all_values[7]	auto[1]	auto[1]	275	1			T13	2		T18	2		T26	4
all_values[8]	auto[0]	auto[0]	24794	1			T11	6		T12	6		T13	1
all_values[8]	auto[0]	auto[1]	12159	1			T1	2		T2	2		T5	2
all_values[8]	auto[1]	auto[0]	26513	1			T10	1		T13	12		T16	1
all_values[8]	auto[1]	auto[1]	11258	1			T6	1		T10	3		T13	13