Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total tests in report: 1315
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
75.30 75.30 94.17 94.17 76.24 76.24 93.31 93.31 90.28 90.28 94.36 94.36 3.43 3.43 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_loopback.3163191088
81.74 6.44 98.29 4.12 89.65 13.41 96.21 2.90 95.14 4.86 97.03 2.67 14.11 10.68 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1595951912
84.46 2.72 98.29 0.00 89.65 0.00 96.21 0.00 95.14 0.00 97.33 0.30 30.14 16.03 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_stress_all.2478479572
86.47 2.01 98.29 0.00 89.65 0.00 96.21 0.00 95.14 0.00 97.33 0.00 42.20 12.06 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_stress_all.4111728099
88.29 1.82 98.59 0.30 93.41 3.76 96.46 0.25 96.30 1.16 97.33 0.00 47.64 5.44 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_intr.3461924574
89.64 1.35 98.99 0.40 95.76 2.35 97.47 1.01 98.15 1.85 97.33 0.00 50.15 2.51 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.1823482280
90.85 1.20 98.99 0.00 95.76 0.00 97.47 0.00 98.15 0.00 97.33 0.00 57.37 7.23 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2522553605
91.80 0.95 98.99 0.00 95.76 0.00 97.47 0.00 98.15 0.00 97.33 0.00 63.08 5.71 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.1638395750
92.73 0.93 98.99 0.00 96.00 0.24 97.47 0.00 98.15 0.00 97.33 0.00 68.41 5.33 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_stress_all.2077030985
93.51 0.78 98.99 0.00 96.00 0.00 97.47 0.00 98.15 0.00 97.33 0.00 73.09 4.67 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_stress_all.3685260261
94.08 0.58 98.99 0.00 96.00 0.00 97.47 0.00 98.15 0.00 97.33 0.00 76.54 3.45 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_stress_all.1884079553
94.64 0.56 99.10 0.10 96.35 0.35 99.75 2.27 98.38 0.23 97.63 0.30 76.65 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_sec_cm.1025966804
95.10 0.46 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 97.63 0.00 79.41 2.75 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_fifo_full.578436074
95.47 0.37 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 97.63 0.00 81.62 2.21 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_stress_all.1442104841
95.84 0.37 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 97.63 0.00 83.81 2.19 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_stress_all.2476867174
96.13 0.30 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 1.78 83.81 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1451890943
96.42 0.29 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 0.00 85.55 1.74 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.3728894227
96.71 0.29 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 0.00 87.29 1.74 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2307440329
96.94 0.23 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 0.00 88.67 1.38 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_stress_all.1788222196
97.13 0.19 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 0.00 89.79 1.13 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1586891301
97.31 0.18 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 0.00 90.88 1.08 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1789340281
97.47 0.16 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 0.00 91.83 0.95 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.297888752
97.61 0.14 99.10 0.00 96.35 0.00 99.75 0.00 98.38 0.00 99.41 0.00 92.68 0.86 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_fifo_full.3604702505
97.74 0.12 99.10 0.00 96.94 0.59 99.75 0.00 98.38 0.00 99.41 0.00 92.84 0.16 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2953411430
97.84 0.10 99.10 0.00 96.94 0.00 99.75 0.00 98.38 0.00 99.41 0.00 93.45 0.61 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_stress_all.4169295682
97.94 0.10 99.10 0.00 97.29 0.35 100.00 0.25 98.38 0.00 99.41 0.00 93.45 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_alert_test.2106612352
98.04 0.10 99.10 0.00 97.29 0.00 100.00 0.00 98.38 0.00 99.70 0.30 93.75 0.29 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_reset.47567987
98.11 0.08 99.10 0.00 97.29 0.00 100.00 0.00 98.38 0.00 99.70 0.00 94.20 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_perf.634868754
98.18 0.07 99.10 0.00 97.41 0.12 100.00 0.00 98.38 0.00 99.70 0.00 94.51 0.32 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.2208183681
98.26 0.07 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 99.70 0.00 94.94 0.43 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.1004344483
98.30 0.05 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.30 94.94 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3087107214
98.35 0.05 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.24 0.29 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.1954025766
98.40 0.05 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.53 0.29 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_noise_filter.2777146684
98.45 0.05 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.80 0.27 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.572819466
98.49 0.04 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.05 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1040433814
98.52 0.03 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.25 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_fifo_full.4123080876
98.56 0.03 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.46 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.2252731663
98.59 0.03 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.66 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.4165819355
98.62 0.03 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.84 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_stress_all.1193190916
98.65 0.03 99.10 0.00 97.53 0.12 100.00 0.00 98.38 0.00 100.00 0.00 96.88 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.4018668607
98.67 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.04 0.16 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_full.3261650019
98.70 0.02 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.18 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_noise_filter.3902107483
98.72 0.02 99.10 0.00 97.65 0.12 100.00 0.00 98.38 0.00 100.00 0.00 97.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2762911351
98.74 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.29 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/146.uart_fifo_reset.2620761455
98.75 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.40 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1581854576
98.77 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.52 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_stress_all.3971036141
98.79 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.63 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_perf.934763501
98.81 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.74 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/81.uart_fifo_reset.3554818640
98.83 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.83 0.09 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1952699789
98.84 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.92 0.09 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_fifo_reset.2954316260
98.86 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.01 0.09 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1054589361
98.87 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.08 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/109.uart_fifo_reset.1285066514
98.88 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.15 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/112.uart_fifo_reset.686089890
98.89 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.22 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/123.uart_fifo_reset.1303568837
98.90 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.28 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/131.uart_fifo_reset.1506027241
98.91 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.35 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_fifo_reset.1678628732
98.92 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.42 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/270.uart_fifo_reset.743134065
98.93 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.49 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.3833630537
98.95 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.55 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.2047114481
98.95 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.60 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3104987573
98.96 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.65 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.4159313332
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.69 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/143.uart_fifo_reset.2704055667
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.74 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3126680386
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.78 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2066849427
98.99 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.83 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_tx_rx.3293176393
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.87 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2710029309
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.92 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2369225218
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_fifo_reset.4268338435
99.02 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_fifo_reset.3170859693
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.05 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_intr.3054583416
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.07 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.684006664
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.10 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/106.uart_fifo_reset.4176436611
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.12 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/114.uart_fifo_reset.3558074826
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.14 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_noise_filter.641002901
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.16 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/121.uart_fifo_reset.637428947
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.19 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/124.uart_fifo_reset.2237736890
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.21 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1557157949
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.23 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/172.uart_fifo_reset.3539709757
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.25 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1943500807
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.28 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3878906929
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.30 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3345909520
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.32 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3038791994
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.35 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1566804154
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.37 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.234789910
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.39 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/281.uart_fifo_reset.918334384
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.41 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1341988291
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.44 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2875692413
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.46 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/50.uart_fifo_reset.2312197873
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.48 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/51.uart_fifo_reset.1454976248

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2778115928
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1128969289
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1803930995
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.4109045183
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1212602400
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.161656595
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.1922561974
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3594936446
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.1089093064
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.2293217388
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.235594208
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.4285414618
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.1078118026
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.850450040
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1195859586
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3147084711
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.2704128567
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3836284317
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3464380024
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1514965943
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1867752348
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1274751102
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3299047500
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.944790061
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1612795845
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3014798309
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.2966929426
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.553752537
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.4119087322
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.4008373925
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3473993342
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3790130941
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3586740387
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.814299818
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2048604597
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2622728993
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3247133249
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.788285069
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.948773466
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.730634132
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1514764155
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1743813720
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2424992751
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1288917154
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2464425044
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4107276211
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3411190928
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.41170001
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2659682580
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.338323070
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2522117380
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.276418142
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.511420566
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.3486550158
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1810320879
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.759297845
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2485696054
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3179970196
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.1171023053
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4030091155
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2231618264
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.13401156
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3202173359
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2456012042
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3691604981
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1720322792
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.158380740
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4033238495
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3141842521
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2549200484
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3251728138
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.707443248
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.835896095
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3088480274
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3379831024
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2721833679
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.4076149696
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.449794431
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.932222338
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.205757113
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2449092367
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1802429872
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.4203973510
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2845256147
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1329449839
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1723773474
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.613475841
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1150245201
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2805825860
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1956939845
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1453192386
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.4186855562
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.1774851269
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2176702158
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.3112728721
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2457160336
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.1320623635
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3161017412
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.324055611
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.2552868363
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3716358602
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1077989000
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.416232371
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.637355446
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2727206598
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.1754986547
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3590523838
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3180295914
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1714739192
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.4063874207
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1440702750
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2411184587
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2643470769
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1770443148
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.1955536937
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3861127492
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.70604258
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.319833173
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.400031359
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2559249555
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2049810167
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2250284582
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3130878921
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.884896649
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.871508781
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3055997553
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1772115355
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3900280812
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.493361722
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2553604179
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.1368031061
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3683475388
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1672444504
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.4088613420
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2498851055
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.4146936621
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1392750888
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2495306950
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1471556363
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3573860635
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4146873830
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2981529175
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.105333683
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1047344271
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.2310784769
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/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/76.uart_fifo_reset.558087009
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/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3261442614
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/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2852923151
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/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/79.uart_fifo_reset.3592721410
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/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_full.2419368079
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1006443078
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_reset.441861549
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_intr.2588458756
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2439956290
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_loopback.1422732608
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_noise_filter.2206992407
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_perf.3664456166
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_oversample.785344951
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1567485035
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_smoke.3874535316
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1804266313
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_tx_rx.3250309776
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/80.uart_fifo_reset.450654871
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2562872105
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.17842083
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1035634842
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.4096050051
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/83.uart_fifo_reset.324453788
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2066163048
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1833004436
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.2669981902
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/85.uart_fifo_reset.3751033248
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.857013023
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/86.uart_fifo_reset.2020131776
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.192900267
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/87.uart_fifo_reset.61923729
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3725061389
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/88.uart_fifo_reset.3230544497
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3315254760
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2049775309
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.3195830562
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_alert_test.204102106
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.240793693
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_fifo_reset.3228853155
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_intr.2671184442
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.470391164
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_loopback.923418346
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_noise_filter.552389771
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_perf.2315041881
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_oversample.4205599480
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3850772656
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.3328232304
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_smoke.3460179006
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_stress_all.3837601218
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/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1301010745
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_tx_rx.3215841150
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/90.uart_fifo_reset.1464359448
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.230971149
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/91.uart_fifo_reset.3147327005
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.3466057787
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/92.uart_fifo_reset.1364353145
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1812825863
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/93.uart_fifo_reset.46383140
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2369328124
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2977885696
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.2851828221
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/95.uart_fifo_reset.399993436
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.3672107801
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1420935037
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.3867454412
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/97.uart_fifo_reset.1483351646
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2314814045
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/98.uart_fifo_reset.201304690
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.1244874794
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/99.uart_fifo_reset.619128977
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.1003332204



Total test records in report: 1315
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_smoke.521498758 Aug 23 03:23:01 AM UTC 24 Aug 23 03:23:03 AM UTC 24 289314580 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.3741487707 Aug 23 03:23:02 AM UTC 24 Aug 23 03:23:04 AM UTC 24 5257218129 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_sec_cm.1025966804 Aug 23 03:23:04 AM UTC 24 Aug 23 03:23:06 AM UTC 24 238035482 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_alert_test.2106612352 Aug 23 03:23:05 AM UTC 24 Aug 23 03:23:07 AM UTC 24 58465662 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_smoke.2949177131 Aug 23 03:23:07 AM UTC 24 Aug 23 03:23:09 AM UTC 24 543150368 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_loopback.3163191088 Aug 23 03:23:03 AM UTC 24 Aug 23 03:23:10 AM UTC 24 3556823178 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_rx_oversample.1355498672 Aug 23 03:23:11 AM UTC 24 Aug 23 03:23:16 AM UTC 24 1862988600 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.1233818925 Aug 23 03:23:02 AM UTC 24 Aug 23 03:23:17 AM UTC 24 38848762183 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1542316560 Aug 23 03:23:18 AM UTC 24 Aug 23 03:23:21 AM UTC 24 1593501164 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_noise_filter.2069691810 Aug 23 03:23:17 AM UTC 24 Aug 23 03:23:26 AM UTC 24 51871637467 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.1823482280 Aug 23 03:23:08 AM UTC 24 Aug 23 03:23:26 AM UTC 24 47484487385 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.2655146913 Aug 23 03:23:24 AM UTC 24 Aug 23 03:23:28 AM UTC 24 863383521 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_fifo_reset.799629527 Aug 23 03:23:01 AM UTC 24 Aug 23 03:23:31 AM UTC 24 19589970664 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2378861845 Aug 23 03:23:01 AM UTC 24 Aug 23 03:23:31 AM UTC 24 4688078765 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_sec_cm.208746513 Aug 23 03:23:30 AM UTC 24 Aug 23 03:23:32 AM UTC 24 145839903 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_loopback.146634421 Aug 23 03:23:26 AM UTC 24 Aug 23 03:23:32 AM UTC 24 4055479541 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1595951912 Aug 23 03:23:04 AM UTC 24 Aug 23 03:23:33 AM UTC 24 5485423185 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_alert_test.3645448882 Aug 23 03:23:32 AM UTC 24 Aug 23 03:23:33 AM UTC 24 56896079 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_smoke.2564681583 Aug 23 03:23:32 AM UTC 24 Aug 23 03:23:34 AM UTC 24 264657979 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_rx_oversample.3262792330 Aug 23 03:23:35 AM UTC 24 Aug 23 03:23:40 AM UTC 24 2653452107 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_reset.47567987 Aug 23 03:23:10 AM UTC 24 Aug 23 03:23:42 AM UTC 24 72583027118 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_fifo_full.1289961825 Aug 23 03:23:01 AM UTC 24 Aug 23 03:23:43 AM UTC 24 39180492537 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_full.2508331763 Aug 23 03:23:08 AM UTC 24 Aug 23 03:23:44 AM UTC 24 154887773027 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.1460106547 Aug 23 03:23:34 AM UTC 24 Aug 23 03:23:47 AM UTC 24 19444322749 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.37253781 Aug 23 03:23:21 AM UTC 24 Aug 23 03:23:49 AM UTC 24 114205485865 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_intr.1478437886 Aug 23 03:23:41 AM UTC 24 Aug 23 03:23:49 AM UTC 24 16377539068 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_fifo_full.2018371882 Aug 23 03:23:33 AM UTC 24 Aug 23 03:23:50 AM UTC 24 47084227397 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.2917166585 Aug 23 03:23:43 AM UTC 24 Aug 23 03:23:52 AM UTC 24 5604025017 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_sec_cm.2689831830 Aug 23 03:23:53 AM UTC 24 Aug 23 03:23:55 AM UTC 24 68757733 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_alert_test.1313230979 Aug 23 03:23:55 AM UTC 24 Aug 23 03:23:56 AM UTC 24 49141676 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_smoke.583400279 Aug 23 03:23:57 AM UTC 24 Aug 23 03:23:59 AM UTC 24 450269029 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3087395923 Aug 23 03:23:44 AM UTC 24 Aug 23 03:23:59 AM UTC 24 14499799683 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_loopback.957078417 Aug 23 03:23:47 AM UTC 24 Aug 23 03:24:01 AM UTC 24 6626058113 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1712598177 Aug 23 03:23:51 AM UTC 24 Aug 23 03:24:04 AM UTC 24 2158559664 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_fifo_reset.3824531585 Aug 23 03:23:34 AM UTC 24 Aug 23 03:24:07 AM UTC 24 120512843096 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_stress_all.3442464957 Aug 23 03:23:52 AM UTC 24 Aug 23 03:24:09 AM UTC 24 31008277591 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_rx_oversample.2523942263 Aug 23 03:24:06 AM UTC 24 Aug 23 03:24:09 AM UTC 24 1374745473 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_intr.1736437989 Aug 23 03:23:13 AM UTC 24 Aug 23 03:24:10 AM UTC 24 38372209032 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.794084904 Aug 23 03:24:10 AM UTC 24 Aug 23 03:24:15 AM UTC 24 42938737705 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_tx_rx.4151267456 Aug 23 03:23:01 AM UTC 24 Aug 23 03:24:17 AM UTC 24 90787660347 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2004266772 Aug 23 03:24:16 AM UTC 24 Aug 23 03:24:19 AM UTC 24 673769991 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.684006664 Aug 23 03:23:01 AM UTC 24 Aug 23 03:24:20 AM UTC 24 54045927363 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_loopback.102538033 Aug 23 03:24:18 AM UTC 24 Aug 23 03:24:24 AM UTC 24 11857683776 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_noise_filter.4214044356 Aug 23 03:23:43 AM UTC 24 Aug 23 03:24:26 AM UTC 24 196649214396 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.4276829988 Aug 23 03:24:01 AM UTC 24 Aug 23 03:24:28 AM UTC 24 36089601333 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_sec_cm.1113577571 Aug 23 03:24:27 AM UTC 24 Aug 23 03:24:28 AM UTC 24 125852772 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_alert_test.1717788536 Aug 23 03:24:29 AM UTC 24 Aug 23 03:24:31 AM UTC 24 16294747 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_smoke.3564615146 Aug 23 03:24:29 AM UTC 24 Aug 23 03:24:32 AM UTC 24 531805838 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_noise_filter.898929010 Aug 23 03:25:23 AM UTC 24 Aug 23 03:25:49 AM UTC 24 32445428791 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_tx_rx.1990478898 Aug 23 03:24:00 AM UTC 24 Aug 23 03:24:36 AM UTC 24 24926225565 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2723814527 Aug 23 03:24:05 AM UTC 24 Aug 23 03:24:37 AM UTC 24 43253627324 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_fifo_full.92720727 Aug 23 03:24:33 AM UTC 24 Aug 23 03:24:39 AM UTC 24 7496249692 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.612117358 Aug 23 03:24:11 AM UTC 24 Aug 23 03:24:39 AM UTC 24 23526306680 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1040433814 Aug 23 03:23:44 AM UTC 24 Aug 23 03:24:42 AM UTC 24 35242547074 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_noise_filter.2646855576 Aug 23 03:23:02 AM UTC 24 Aug 23 03:24:46 AM UTC 24 67341928586 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_rx_oversample.393482048 Aug 23 03:24:38 AM UTC 24 Aug 23 03:24:48 AM UTC 24 2012675447 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3104987573 Aug 23 03:23:02 AM UTC 24 Aug 23 03:24:50 AM UTC 24 166007801942 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.1063677730 Aug 23 03:24:23 AM UTC 24 Aug 23 03:24:53 AM UTC 24 4805094210 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.3140375643 Aug 23 03:24:42 AM UTC 24 Aug 23 03:24:55 AM UTC 24 35841423537 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_loopback.832841157 Aug 23 03:24:50 AM UTC 24 Aug 23 03:24:59 AM UTC 24 3933206262 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_noise_filter.3346348708 Aug 23 03:24:40 AM UTC 24 Aug 23 03:25:00 AM UTC 24 12401520375 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3700360683 Aug 23 03:24:48 AM UTC 24 Aug 23 03:25:01 AM UTC 24 7307641768 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.178444544 Aug 23 03:24:46 AM UTC 24 Aug 23 03:25:01 AM UTC 24 19431892786 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_alert_test.959742252 Aug 23 03:25:02 AM UTC 24 Aug 23 03:25:03 AM UTC 24 11607482 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_sec_cm.3314545883 Aug 23 03:25:02 AM UTC 24 Aug 23 03:25:03 AM UTC 24 38000442 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3793643846 Aug 23 03:24:37 AM UTC 24 Aug 23 03:25:08 AM UTC 24 61812033861 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_intr.3461924574 Aug 23 03:24:39 AM UTC 24 Aug 23 03:25:11 AM UTC 24 56444381156 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_tx_rx.238794343 Aug 23 03:24:32 AM UTC 24 Aug 23 03:25:21 AM UTC 24 31884224622 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_smoke.1896208138 Aug 23 03:25:04 AM UTC 24 Aug 23 03:25:22 AM UTC 24 5816212356 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_tx_rx.3993501487 Aug 23 03:23:07 AM UTC 24 Aug 23 03:25:25 AM UTC 24 65292730469 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_fifo_full.888621229 Aug 23 03:25:09 AM UTC 24 Aug 23 03:25:27 AM UTC 24 32907264180 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_rx_oversample.3518422275 Aug 23 03:25:22 AM UTC 24 Aug 23 03:25:32 AM UTC 24 5159278026 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.1331391076 Aug 23 03:25:33 AM UTC 24 Aug 23 03:25:36 AM UTC 24 632115436 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_stress_all.2478479572 Aug 23 03:23:04 AM UTC 24 Aug 23 03:25:40 AM UTC 24 197390913890 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.550211584 Aug 23 03:25:26 AM UTC 24 Aug 23 03:25:41 AM UTC 24 33437390752 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.1004344483 Aug 23 03:25:12 AM UTC 24 Aug 23 03:25:48 AM UTC 24 248755633768 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.1608443030 Aug 23 03:24:37 AM UTC 24 Aug 23 03:25:50 AM UTC 24 215763238979 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_alert_test.1754506266 Aug 23 03:25:49 AM UTC 24 Aug 23 03:25:51 AM UTC 24 15327450 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_intr.3854066805 Aug 23 03:24:08 AM UTC 24 Aug 23 03:25:51 AM UTC 24 61984248738 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_loopback.3128940590 Aug 23 03:25:35 AM UTC 24 Aug 23 03:25:51 AM UTC 24 9021656074 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_smoke.3566265246 Aug 23 03:25:50 AM UTC 24 Aug 23 03:25:52 AM UTC 24 542748395 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_perf.2165670648 Aug 23 03:23:49 AM UTC 24 Aug 23 03:26:02 AM UTC 24 12205746119 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_tx_rx.3293176393 Aug 23 03:23:32 AM UTC 24 Aug 23 03:26:03 AM UTC 24 95388052390 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_rx_oversample.2866086592 Aug 23 03:25:56 AM UTC 24 Aug 23 03:26:06 AM UTC 24 7063131965 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_intr.2424756549 Aug 23 03:23:01 AM UTC 24 Aug 23 03:26:07 AM UTC 24 134388860561 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.297888752 Aug 23 03:25:28 AM UTC 24 Aug 23 03:26:15 AM UTC 24 46150865582 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_perf.3010403899 Aug 23 03:24:20 AM UTC 24 Aug 23 03:26:17 AM UTC 24 13351825248 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_fifo_full.284539539 Aug 23 03:24:00 AM UTC 24 Aug 23 03:26:18 AM UTC 24 144694738428 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.3704492001 Aug 23 03:25:52 AM UTC 24 Aug 23 03:26:18 AM UTC 24 31873399354 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.3892559946 Aug 23 03:26:15 AM UTC 24 Aug 23 03:26:19 AM UTC 24 1514237279 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_fifo_full.928448477 Aug 23 03:25:51 AM UTC 24 Aug 23 03:26:19 AM UTC 24 252780665626 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.2642240976 Aug 23 03:26:07 AM UTC 24 Aug 23 03:26:22 AM UTC 24 43745301348 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_intr.1893956572 Aug 23 03:26:02 AM UTC 24 Aug 23 03:26:23 AM UTC 24 14319597299 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_alert_test.3504462475 Aug 23 03:26:22 AM UTC 24 Aug 23 03:26:24 AM UTC 24 28255177 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_loopback.2257943597 Aug 23 03:26:18 AM UTC 24 Aug 23 03:26:24 AM UTC 24 9437387951 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_smoke.2886760192 Aug 23 03:26:24 AM UTC 24 Aug 23 03:26:27 AM UTC 24 735626143 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_fifo_reset.2545091226 Aug 23 03:25:53 AM UTC 24 Aug 23 03:26:32 AM UTC 24 48206052730 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_noise_filter.2777146684 Aug 23 03:24:10 AM UTC 24 Aug 23 03:26:50 AM UTC 24 123255574522 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_tx_rx.2769193394 Aug 23 03:26:24 AM UTC 24 Aug 23 03:26:51 AM UTC 24 18906196473 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.767022828 Aug 23 03:26:51 AM UTC 24 Aug 23 03:26:53 AM UTC 24 3749215464 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.3465553089 Aug 23 03:26:08 AM UTC 24 Aug 23 03:26:55 AM UTC 24 36030875220 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.1505859696 Aug 23 03:26:55 AM UTC 24 Aug 23 03:27:00 AM UTC 24 1166899860 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_rx_oversample.1013766330 Aug 23 03:26:36 AM UTC 24 Aug 23 03:27:01 AM UTC 24 4210672553 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.3627833057 Aug 23 03:26:19 AM UTC 24 Aug 23 03:27:02 AM UTC 24 1172338576 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_noise_filter.2453732525 Aug 23 03:26:04 AM UTC 24 Aug 23 03:27:04 AM UTC 24 166447215524 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1793140702 Aug 23 03:25:20 AM UTC 24 Aug 23 03:27:04 AM UTC 24 62188314907 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_tx_rx.733753571 Aug 23 03:25:04 AM UTC 24 Aug 23 03:27:15 AM UTC 24 80028901387 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_loopback.164542672 Aug 23 03:27:00 AM UTC 24 Aug 23 03:27:16 AM UTC 24 8435837347 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_alert_test.3737302495 Aug 23 03:27:18 AM UTC 24 Aug 23 03:27:20 AM UTC 24 43200794 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_smoke.3874535316 Aug 23 03:27:18 AM UTC 24 Aug 23 03:27:20 AM UTC 24 91709527 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.1109172071 Aug 23 03:26:54 AM UTC 24 Aug 23 03:27:20 AM UTC 24 14139863820 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_tx_rx.1376451563 Aug 23 03:25:51 AM UTC 24 Aug 23 03:27:23 AM UTC 24 56105015520 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.3693688254 Aug 23 03:24:56 AM UTC 24 Aug 23 03:27:24 AM UTC 24 39259362512 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_noise_filter.1512756092 Aug 23 03:26:51 AM UTC 24 Aug 23 03:27:30 AM UTC 24 21835223874 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_stress_all.2476867174 Aug 23 03:25:49 AM UTC 24 Aug 23 03:27:30 AM UTC 24 152965652156 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2024747021 Aug 23 03:26:33 AM UTC 24 Aug 23 03:27:31 AM UTC 24 91270144213 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1789340281 Aug 23 03:26:28 AM UTC 24 Aug 23 03:27:31 AM UTC 24 132026075350 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1567485035 Aug 23 03:27:31 AM UTC 24 Aug 23 03:27:36 AM UTC 24 3918220982 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.347979420 Aug 23 03:27:05 AM UTC 24 Aug 23 03:27:37 AM UTC 24 10915342335 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_full.2419368079 Aug 23 03:27:21 AM UTC 24 Aug 23 03:27:38 AM UTC 24 20529694834 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_tx_rx.3250309776 Aug 23 03:27:21 AM UTC 24 Aug 23 03:27:42 AM UTC 24 218239697553 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_loopback.1422732608 Aug 23 03:27:38 AM UTC 24 Aug 23 03:27:44 AM UTC 24 4446649675 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_reset.441861549 Aug 23 03:27:23 AM UTC 24 Aug 23 03:27:46 AM UTC 24 13966070183 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_fifo_full.4243389798 Aug 23 03:26:25 AM UTC 24 Aug 23 03:27:51 AM UTC 24 69874294016 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_alert_test.1799653751 Aug 23 03:27:52 AM UTC 24 Aug 23 03:27:54 AM UTC 24 34557862 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_smoke.3460179006 Aug 23 03:27:54 AM UTC 24 Aug 23 03:27:57 AM UTC 24 475740362 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1804266313 Aug 23 03:27:38 AM UTC 24 Aug 23 03:27:57 AM UTC 24 6595910654 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_perf.1265771662 Aug 23 03:23:27 AM UTC 24 Aug 23 03:28:02 AM UTC 24 10793511538 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_intr.2588458756 Aug 23 03:27:31 AM UTC 24 Aug 23 03:28:03 AM UTC 24 22329418508 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1054589361 Aug 23 03:27:46 AM UTC 24 Aug 23 03:28:05 AM UTC 24 1984005881 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_tx_rx.3215841150 Aug 23 03:27:58 AM UTC 24 Aug 23 03:28:06 AM UTC 24 72684023771 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1006443078 Aug 23 03:27:21 AM UTC 24 Aug 23 03:28:09 AM UTC 24 59856737928 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_noise_filter.2206992407 Aug 23 03:27:31 AM UTC 24 Aug 23 03:28:13 AM UTC 24 169348326530 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.2357992363 Aug 23 03:24:21 AM UTC 24 Aug 23 03:28:15 AM UTC 24 46558128522 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_oversample.785344951 Aug 23 03:27:25 AM UTC 24 Aug 23 03:28:17 AM UTC 24 6512527847 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_intr.1514807778 Aug 23 03:26:50 AM UTC 24 Aug 23 03:28:17 AM UTC 24 269826430517 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_loopback.923418346 Aug 23 03:28:18 AM UTC 24 Aug 23 03:28:21 AM UTC 24 2521040629 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.3328232304 Aug 23 03:28:13 AM UTC 24 Aug 23 03:28:21 AM UTC 24 4211235354 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2307440329 Aug 23 03:27:33 AM UTC 24 Aug 23 03:28:22 AM UTC 24 68353885304 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_stress_all.3837601218 Aug 23 03:28:23 AM UTC 24 Aug 23 03:28:28 AM UTC 24 3430645720 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_alert_test.204102106 Aug 23 03:28:29 AM UTC 24 Aug 23 03:28:30 AM UTC 24 40079217 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1301010745 Aug 23 03:28:17 AM UTC 24 Aug 23 03:28:32 AM UTC 24 7001476936 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_smoke.3006842198 Aug 23 03:28:31 AM UTC 24 Aug 23 03:28:33 AM UTC 24 661795133 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_fifo_reset.3228853155 Aug 23 03:28:05 AM UTC 24 Aug 23 03:28:36 AM UTC 24 11691109253 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_intr.2671184442 Aug 23 03:28:07 AM UTC 24 Aug 23 03:28:39 AM UTC 24 31236235471 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_oversample.4205599480 Aug 23 03:28:07 AM UTC 24 Aug 23 03:28:57 AM UTC 24 5846391852 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_tx_rx.3941735785 Aug 23 03:28:33 AM UTC 24 Aug 23 03:29:05 AM UTC 24 74845278493 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.1638395750 Aug 23 03:25:41 AM UTC 24 Aug 23 03:29:15 AM UTC 24 125848079717 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_fifo_full.3604702505 Aug 23 03:28:34 AM UTC 24 Aug 23 03:29:17 AM UTC 24 90748919366 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_noise_filter.552389771 Aug 23 03:28:09 AM UTC 24 Aug 23 03:29:20 AM UTC 24 94527240179 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.4258663383 Aug 23 03:27:03 AM UTC 24 Aug 23 03:29:21 AM UTC 24 79953912451 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3389293560 Aug 23 03:28:23 AM UTC 24 Aug 23 03:29:21 AM UTC 24 2477033104 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.3799854679 Aug 23 03:29:18 AM UTC 24 Aug 23 03:29:22 AM UTC 24 5935966750 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.373748960 Aug 23 03:29:21 AM UTC 24 Aug 23 03:29:24 AM UTC 24 5578159278 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_loopback.3386801055 Aug 23 03:29:22 AM UTC 24 Aug 23 03:29:25 AM UTC 24 2091775429 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_intr.1165301271 Aug 23 03:29:06 AM UTC 24 Aug 23 03:29:26 AM UTC 24 40039853837 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_noise_filter.3616412864 Aug 23 03:29:16 AM UTC 24 Aug 23 03:29:35 AM UTC 24 12305927585 ps
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T446 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_alert_test.2338082022 Aug 23 03:29:37 AM UTC 24 Aug 23 03:29:38 AM UTC 24 11591400 ps
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T300 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3853661411 Aug 23 03:28:40 AM UTC 24 Aug 23 03:29:49 AM UTC 24 251473294823 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_rx_oversample.3713168383 Aug 23 03:28:58 AM UTC 24 Aug 23 03:29:50 AM UTC 24 6970205643 ps
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T301 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_perf.3664456166 Aug 23 03:27:40 AM UTC 24 Aug 23 03:30:03 AM UTC 24 11059468454 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_fifo_reset.1240205043 Aug 23 03:29:51 AM UTC 24 Aug 23 03:30:05 AM UTC 24 9370671138 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2522553605 Aug 23 03:26:19 AM UTC 24 Aug 23 03:30:08 AM UTC 24 59378109453 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.537234288 Aug 23 03:30:06 AM UTC 24 Aug 23 03:30:09 AM UTC 24 1411704105 ps
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T449 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_loopback.3809340056 Aug 23 03:30:09 AM UTC 24 Aug 23 03:30:11 AM UTC 24 366811591 ps
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T125 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.307323247 Aug 23 03:28:37 AM UTC 24 Aug 23 03:30:14 AM UTC 24 119697849966 ps
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T451 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_smoke.2410191492 Aug 23 03:30:17 AM UTC 24 Aug 23 03:30:20 AM UTC 24 242670080 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.2104788603 Aug 23 03:23:28 AM UTC 24 Aug 23 03:30:29 AM UTC 24 58812647492 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.4159313332 Aug 23 03:30:04 AM UTC 24 Aug 23 03:30:31 AM UTC 24 69310985683 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_noise_filter.841239343 Aug 23 03:29:59 AM UTC 24 Aug 23 03:30:32 AM UTC 24 73347484032 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.2208183681 Aug 23 03:30:12 AM UTC 24 Aug 23 03:30:39 AM UTC 24 14407318824 ps
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T380 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_fifo_reset.3081119785 Aug 23 03:30:33 AM UTC 24 Aug 23 03:30:46 AM UTC 24 27978697902 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_rx_oversample.95205734 Aug 23 03:29:56 AM UTC 24 Aug 23 03:30:52 AM UTC 24 7786433521 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.656260436 Aug 23 03:30:53 AM UTC 24 Aug 23 03:30:59 AM UTC 24 2909999171 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_tx_rx.2246963234 Aug 23 03:30:21 AM UTC 24 Aug 23 03:30:59 AM UTC 24 42172241143 ps
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T360 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.579607365 Aug 23 03:31:00 AM UTC 24 Aug 23 03:31:03 AM UTC 24 559566270 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_loopback.4241955688 Aug 23 03:31:01 AM UTC 24 Aug 23 03:31:04 AM UTC 24 4062325461 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.2091175028 Aug 23 03:30:00 AM UTC 24 Aug 23 03:31:23 AM UTC 24 85432003077 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3850772656 Aug 23 03:28:17 AM UTC 24 Aug 23 03:31:24 AM UTC 24 67798534201 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_perf.634868754 Aug 23 03:26:18 AM UTC 24 Aug 23 03:31:26 AM UTC 24 25626838856 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_alert_test.3828765751 Aug 23 03:31:26 AM UTC 24 Aug 23 03:31:28 AM UTC 24 12939745 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_smoke.1635003544 Aug 23 03:31:28 AM UTC 24 Aug 23 03:31:37 AM UTC 24 5574855995 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_noise_filter.641002901 Aug 23 03:30:47 AM UTC 24 Aug 23 03:31:40 AM UTC 24 114408910324 ps
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T292 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.4259852594 Aug 23 03:31:00 AM UTC 24 Aug 23 03:31:44 AM UTC 24 26581172021 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_tx_rx.3115457874 Aug 23 03:31:37 AM UTC 24 Aug 23 03:31:52 AM UTC 24 35801965139 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_stress_all.4111728099 Aug 23 03:25:00 AM UTC 24 Aug 23 03:31:58 AM UTC 24 367801449019 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3495216974 Aug 23 03:31:53 AM UTC 24 Aug 23 03:31:58 AM UTC 24 1888501922 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3599938750 Aug 23 03:31:23 AM UTC 24 Aug 23 03:32:01 AM UTC 24 7854876342 ps
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T342 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.4246335431 Aug 23 03:31:43 AM UTC 24 Aug 23 03:32:07 AM UTC 24 29735056496 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_intr.3925768457 Aug 23 03:31:59 AM UTC 24 Aug 23 03:32:10 AM UTC 24 17617309148 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.2698066617 Aug 23 03:32:08 AM UTC 24 Aug 23 03:32:11 AM UTC 24 3045393914 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1586891301 Aug 23 03:30:32 AM UTC 24 Aug 23 03:32:11 AM UTC 24 127244032963 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_stress_all.1262200622 Aug 23 03:31:24 AM UTC 24 Aug 23 03:32:23 AM UTC 24 72102296180 ps
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T332 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_full.3261650019 Aug 23 03:31:41 AM UTC 24 Aug 23 03:32:29 AM UTC 24 29825799504 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_stress_all.3685260261 Aug 23 03:27:48 AM UTC 24 Aug 23 03:32:29 AM UTC 24 641755531840 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_alert_test.486134995 Aug 23 03:32:29 AM UTC 24 Aug 23 03:32:31 AM UTC 24 23301839 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_smoke.869878719 Aug 23 03:32:30 AM UTC 24 Aug 23 03:32:34 AM UTC 24 714598017 ps
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T357 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.46856042 Aug 23 03:29:50 AM UTC 24 Aug 23 03:32:37 AM UTC 24 109908189353 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1165009743 Aug 23 03:32:36 AM UTC 24 Aug 23 03:32:47 AM UTC 24 24897851475 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.470391164 Aug 23 03:28:23 AM UTC 24 Aug 23 03:32:49 AM UTC 24 50562251227 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_noise_filter.990899722 Aug 23 03:31:59 AM UTC 24 Aug 23 03:33:01 AM UTC 24 87320265076 ps
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T132 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1952699789 Aug 23 03:31:45 AM UTC 24 Aug 23 03:33:11 AM UTC 24 62646354285 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_perf.4221731012 Aug 23 03:29:22 AM UTC 24 Aug 23 03:33:11 AM UTC 24 10588381803 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_perf.1865693575 Aug 23 03:30:09 AM UTC 24 Aug 23 03:33:12 AM UTC 24 12867308507 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.472069383 Aug 23 03:33:09 AM UTC 24 Aug 23 03:33:14 AM UTC 24 5818657911 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.469900055 Aug 23 03:33:12 AM UTC 24 Aug 23 03:33:14 AM UTC 24 824034789 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_fifo_reset.2954316260 Aug 23 03:32:38 AM UTC 24 Aug 23 03:33:17 AM UTC 24 20093368015 ps
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