Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2543

1

T1

1

T2

1

T3

21

auto[UartRx]

2543

1

T1

1

T2

1

T3

21

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4459	1			T1	2		T2	2		T3	42
values[1]	38	1			T391	1		T87	1		T392	1
values[2]	48	1			T13	2		T393	1		T392	2
values[3]	51	1			T13	2		T28	1		T36	1
values[4]	41	1			T27	1		T33	2		T35	2
values[5]	57	1			T36	2		T38	1		T39	1
values[6]	55	1			T13	1		T33	2		T34	1
values[7]	70	1			T13	1		T27	1		T34	3
values[8]	59	1			T28	1		T34	1		T38	1
values[9]	76	1			T13	1		T33	1		T35	1
values[10]	87	1			T13	1		T28	2		T33	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2326	1			T1	1		T2	1		T3	21
auto[UartTx]	values[1]	11	1			T394	1		T395	1		T396	1
auto[UartTx]	values[2]	17	1			T89	1		T397	1		T92	1
auto[UartTx]	values[3]	12	1			T392	2		T398	1		T399	1
auto[UartTx]	values[4]	11	1			T27	1		T33	1		T35	1
auto[UartTx]	values[5]	18	1			T391	1		T105	1		T356	1
auto[UartTx]	values[6]	19	1			T33	1		T35	1		T38	1
auto[UartTx]	values[7]	33	1			T13	1		T27	1		T34	2
auto[UartTx]	values[8]	26	1			T87	1		T105	1		T400	1
auto[UartTx]	values[9]	21	1			T356	1		T401	1		T394	1
auto[UartTx]	values[10]	34	1			T33	1		T35	1		T37	1
auto[UartRx]	values[0]	2133	1			T1	1		T2	1		T3	21
auto[UartRx]	values[1]	27	1			T391	1		T87	1		T392	1
auto[UartRx]	values[2]	31	1			T13	2		T393	1		T392	2
auto[UartRx]	values[3]	39	1			T13	2		T28	1		T36	1
auto[UartRx]	values[4]	30	1			T33	1		T35	1		T37	1
auto[UartRx]	values[5]	39	1			T36	2		T38	1		T39	1
auto[UartRx]	values[6]	36	1			T13	1		T33	1		T34	1
auto[UartRx]	values[7]	37	1			T34	1		T38	1		T39	2
auto[UartRx]	values[8]	33	1			T28	1		T34	1		T38	1
auto[UartRx]	values[9]	55	1			T13	1		T33	1		T35	1
auto[UartRx]	values[10]	53	1			T13	1		T28	2		T33	1