Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1848	1			T6	9		T7	3		T8	1
auto[BaudRate115200]	1492	1			T2	1		T6	3		T10	2
auto[BaudRate230400]	1465	1			T5	2		T10	1		T24	6
auto[BaudRate128Kbps]	1456	1			T2	1		T8	1		T11	1
auto[BaudRate256Kbps]	1558	1			T1	1		T9	1		T11	1
auto[BaudRate1Mbps]	1334	1			T1	1		T9	1		T11	2
auto[BaudRate1p5Mbps]	1064	1			T6	6		T12	1		T24	6

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1339	1			T8	2		T15	6		T286	2
freqs[25]	784	1			T19	1		T95	10		T260	6
freqs[48]	458	1			T43	12		T111	5		T351	2
freqs[50]	377	1			T115	7		T124	24		T402	36
freqs[100]	981	1			T6	18		T40	2		T25	45

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	235	1			T8	1		T15	2		T403	13
auto[BaudRate9600]	freqs[25]	121	1			T95	1		T260	1		T298	1
auto[BaudRate9600]	freqs[48]	59	1			T43	4		T351	1		T254	1
auto[BaudRate9600]	freqs[50]	58	1			T124	4		T402	6		T125	2
auto[BaudRate9600]	freqs[100]	189	1			T6	9		T25	9		T26	1
auto[BaudRate115200]	freqs[24]	213	1			T15	2		T316	1		T273	1
auto[BaudRate115200]	freqs[25]	116	1			T95	2		T298	2		T119	2
auto[BaudRate115200]	freqs[48]	62	1			T43	5		T111	1		T116	4
auto[BaudRate115200]	freqs[50]	55	1			T115	1		T124	5		T402	3
auto[BaudRate115200]	freqs[100]	137	1			T6	3		T25	12		T22	1
auto[BaudRate230400]	freqs[24]	227	1			T34	3		T301	2		T317	1
auto[BaudRate230400]	freqs[25]	127	1			T19	1		T95	2		T260	1
auto[BaudRate230400]	freqs[48]	53	1			T43	1		T111	2		T351	1
auto[BaudRate230400]	freqs[50]	46	1			T115	2		T124	2		T402	3
auto[BaudRate230400]	freqs[100]	106	1			T26	1		T404	9		T328	1
auto[BaudRate128Kbps]	freqs[24]	193	1			T8	1		T273	1		T34	4
auto[BaudRate128Kbps]	freqs[25]	128	1			T118	1		T298	5		T313	1
auto[BaudRate128Kbps]	freqs[48]	63	1			T43	1		T116	1		T97	1
auto[BaudRate128Kbps]	freqs[50]	53	1			T115	2		T124	2		T402	3
auto[BaudRate128Kbps]	freqs[100]	124	1			T25	3		T22	1		T26	1
auto[BaudRate256Kbps]	freqs[24]	198	1			T15	1		T286	2		T273	3
auto[BaudRate256Kbps]	freqs[25]	104	1			T95	3		T260	2		T118	1
auto[BaudRate256Kbps]	freqs[48]	69	1			T111	1		T116	1		T254	4
auto[BaudRate256Kbps]	freqs[50]	52	1			T124	3		T402	9		T125	1
auto[BaudRate256Kbps]	freqs[100]	154	1			T40	1		T25	9		T26	1
auto[BaudRate1Mbps]	freqs[24]	184	1			T316	1		T34	1		T257	2
auto[BaudRate1Mbps]	freqs[25]	131	1			T95	2		T260	2		T118	2
auto[BaudRate1Mbps]	freqs[48]	79	1			T43	1		T116	2		T97	2
auto[BaudRate1Mbps]	freqs[50]	61	1			T115	1		T124	5		T402	6
auto[BaudRate1Mbps]	freqs[100]	118	1			T40	1		T25	9		T45	1
auto[BaudRate1p5Mbps]	freqs[25]	57	1			T298	1		T137	1		T308	1
auto[BaudRate1p5Mbps]	freqs[48]	73	1			T111	1		T116	1		T254	3
auto[BaudRate1p5Mbps]	freqs[50]	52	1			T115	1		T124	3		T402	6
auto[BaudRate1p5Mbps]	freqs[100]	153	1			T6	6		T25	3		T26	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded