Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	22920102	1			T6	4		T7	1		T10	11
all_levels[1]	143821	1			T10	3		T12	1		T15	11
all_levels[2]	1803	1			T15	6		T109	2		T110	1
all_levels[3]	749	1			T15	3		T16	1		T111	1
all_levels[4]	540	1			T11	1		T15	4		T16	1
all_levels[5]	393	1			T15	1		T18	1		T43	2
all_levels[6]	323	1			T15	1		T16	1		T95	1
all_levels[7]	250	1			T16	2		T26	2		T112	1
all_levels[8]	222	1			T11	1		T16	2		T95	1
all_levels[9]	210	1			T11	1		T16	3		T95	2
all_levels[10]	174	1			T17	1		T46	2		T98	1
all_levels[11]	151	1			T43	2		T98	1		T47	1
all_levels[12]	151	1			T11	1		T41	1		T95	1
all_levels[13]	138	1			T16	2		T113	1		T114	1
all_levels[14]	121	1			T16	2		T17	1		T95	1
all_levels[15]	115	1			T16	1		T114	2		T46	1
all_levels[16]	86	1			T11	1		T95	1		T114	1
all_levels[17]	100	1			T115	1		T26	2		T46	1
all_levels[18]	84	1			T16	1		T115	1		T116	1
all_levels[19]	75	1			T112	2		T98	2		T117	1
all_levels[20]	68	1			T95	1		T26	1		T46	1
all_levels[21]	56	1			T12	1		T118	1		T47	1
all_levels[22]	46	1			T46	1		T47	1		T119	1
all_levels[23]	48	1			T46	1		T120	2		T121	1
all_levels[24]	54	1			T95	1		T115	1		T46	1
all_levels[25]	42	1			T47	1		T120	1		T122	1
all_levels[26]	51	1			T95	2		T46	1		T98	1
all_levels[27]	47	1			T112	1		T47	1		T123	1
all_levels[28]	33	1			T26	1		T124	2		T125	1
all_levels[29]	26	1			T26	2		T120	1		T99	1
all_levels[30]	44	1			T15	1		T46	1		T126	1
all_levels[31]	22	1			T118	1		T127	1		T128	1
all_levels[32]	23	1			T11	1		T116	1		T129	1
all_levels[33]	29	1			T18	1		T47	1		T130	1
all_levels[34]	30	1			T97	1		T126	1		T122	1
all_levels[35]	20	1			T47	1		T131	1		T103	1
all_levels[36]	17	1			T132	1		T133	1		T134	2
all_levels[37]	14	1			T135	1		T136	1		T137	1
all_levels[38]	19	1			T15	1		T16	1		T26	1
all_levels[39]	19	1			T136	1		T138	1		T139	1
all_levels[40]	23	1			T11	1		T118	1		T137	1
all_levels[41]	17	1			T118	1		T140	1		T121	1
all_levels[42]	17	1			T118	1		T46	1		T132	1
all_levels[43]	18	1			T116	1		T141	1		T129	2
all_levels[44]	13	1			T46	1		T142	2		T143	1
all_levels[45]	13	1			T98	1		T130	1		T144	3
all_levels[46]	12	1			T145	1		T146	1		T147	1
all_levels[47]	6	1			T120	1		T145	1		T148	1
all_levels[48]	10	1			T135	1		T122	1		T149	1
all_levels[49]	11	1			T124	1		T99	1		T150	1
all_levels[50]	10	1			T11	1		T120	2		T150	1
all_levels[51]	9	1			T116	1		T151	2		T148	1
all_levels[52]	6	1			T142	1		T152	1		T153	1
all_levels[53]	5	1			T15	3		T134	1		T154	1
all_levels[54]	8	1			T122	1		T155	1		T156	1
all_levels[55]	14	1			T11	1		T103	1		T157	3
all_levels[56]	5	1			T118	1		T158	1		T159	1
all_levels[57]	8	1			T160	1		T26	1		T131	3
all_levels[58]	7	1			T17	1		T155	1		T161	1
all_levels[59]	15	1			T162	2		T163	1		T164	1
all_levels[60]	8	1			T110	1		T140	1		T141	1
all_levels[61]	4	1			T11	1		T47	1		T99	1
all_levels[62]	5	1			T41	1		T165	1		T158	1
all_levels[63]	10	1			T17	1		T166	1		T167	1
all_levels[64]	83	1			T16	3		T17	1		T18	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23066843

1

T10

14

T11

23

T12

24

auto[1]

3810

1

T6

4

T7

1

T12

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[29]]	[auto[1]]	0	1	1
[all_levels[37] , all_levels[38]]	[auto[1]]	--	--	2
[all_levels[47] , all_levels[48] , all_levels[49]]	[auto[1]]	--	--	3
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	22916727	1			T10	11		T11	13		T12	22
all_levels[0]	auto[1]	3375	1			T6	4		T7	1		T12	4
all_levels[1]	auto[0]	143732	1			T10	3		T12	1		T15	9
all_levels[1]	auto[1]	89	1			T15	2		T162	1		T124	1
all_levels[2]	auto[0]	1773	1			T15	6		T109	2		T110	1
all_levels[2]	auto[1]	30	1			T168	2		T169	1		T170	2
all_levels[3]	auto[0]	732	1			T15	3		T16	1		T111	1
all_levels[3]	auto[1]	17	1			T171	1		T172	2		T173	1
all_levels[4]	auto[0]	519	1			T11	1		T15	4		T16	1
all_levels[4]	auto[1]	21	1			T126	1		T169	2		T174	1
all_levels[5]	auto[0]	381	1			T15	1		T18	1		T43	2
all_levels[5]	auto[1]	12	1			T132	2		T175	1		T176	1
all_levels[6]	auto[0]	307	1			T15	1		T16	1		T95	1
all_levels[6]	auto[1]	16	1			T177	1		T178	1		T179	3
all_levels[7]	auto[0]	240	1			T16	2		T26	2		T112	1
all_levels[7]	auto[1]	10	1			T180	3		T181	1		T182	1
all_levels[8]	auto[0]	208	1			T11	1		T16	2		T95	1
all_levels[8]	auto[1]	14	1			T183	1		T184	1		T185	1
all_levels[9]	auto[0]	197	1			T11	1		T16	3		T95	2
all_levels[9]	auto[1]	13	1			T186	2		T187	1		T188	1
all_levels[10]	auto[0]	166	1			T17	1		T46	2		T98	1
all_levels[10]	auto[1]	8	1			T189	1		T190	2		T191	1
all_levels[11]	auto[0]	144	1			T43	2		T98	1		T47	1
all_levels[11]	auto[1]	7	1			T192	2		T193	1		T194	1
all_levels[12]	auto[0]	142	1			T11	1		T41	1		T95	1
all_levels[12]	auto[1]	9	1			T124	1		T175	2		T156	1
all_levels[13]	auto[0]	130	1			T16	2		T113	1		T114	1
all_levels[13]	auto[1]	8	1			T189	1		T195	1		T106	1
all_levels[14]	auto[0]	108	1			T16	2		T17	1		T95	1
all_levels[14]	auto[1]	13	1			T177	1		T196	2		T197	1
all_levels[15]	auto[0]	107	1			T16	1		T114	1		T46	1
all_levels[15]	auto[1]	8	1			T114	1		T194	1		T198	2
all_levels[16]	auto[0]	84	1			T11	1		T95	1		T114	1
all_levels[16]	auto[1]	2	1			T199	1		T200	1		-	-
all_levels[17]	auto[0]	82	1			T115	1		T26	2		T46	1
all_levels[17]	auto[1]	18	1			T201	1		T202	5		T203	3
all_levels[18]	auto[0]	78	1			T16	1		T115	1		T116	1
all_levels[18]	auto[1]	6	1			T159	1		T204	1		T205	1
all_levels[19]	auto[0]	66	1			T112	2		T98	2		T117	1
all_levels[19]	auto[1]	9	1			T206	1		T207	1		T208	2
all_levels[20]	auto[0]	59	1			T95	1		T26	1		T46	1
all_levels[20]	auto[1]	9	1			T132	1		T209	1		T210	1
all_levels[21]	auto[0]	50	1			T12	1		T118	1		T47	1
all_levels[21]	auto[1]	6	1			T211	1		T156	1		T181	2
all_levels[22]	auto[0]	40	1			T46	1		T47	1		T119	1
all_levels[22]	auto[1]	6	1			T212	1		T213	5		-	-
all_levels[23]	auto[0]	41	1			T46	1		T120	2		T121	1
all_levels[23]	auto[1]	7	1			T214	1		T159	4		T215	1
all_levels[24]	auto[0]	48	1			T95	1		T115	1		T46	1
all_levels[24]	auto[1]	6	1			T216	1		T217	2		T218	1
all_levels[25]	auto[0]	38	1			T47	1		T120	1		T122	1
all_levels[25]	auto[1]	4	1			T219	1		T206	2		T220	1
all_levels[26]	auto[0]	47	1			T95	2		T46	1		T98	1
all_levels[26]	auto[1]	4	1			T221	3		T222	1		-	-
all_levels[27]	auto[0]	42	1			T112	1		T47	1		T123	1
all_levels[27]	auto[1]	5	1			T176	2		T223	2		T224	1
all_levels[28]	auto[0]	30	1			T26	1		T124	1		T125	1
all_levels[28]	auto[1]	3	1			T124	1		T202	1		T225	1
all_levels[29]	auto[0]	26	1			T26	2		T120	1		T99	1
all_levels[30]	auto[0]	41	1			T15	1		T46	1		T126	1
all_levels[30]	auto[1]	3	1			T209	1		T226	1		T227	1
all_levels[31]	auto[0]	19	1			T118	1		T127	1		T128	1
all_levels[31]	auto[1]	3	1			T188	1		T228	1		T229	1
all_levels[32]	auto[0]	22	1			T11	1		T116	1		T129	1
all_levels[32]	auto[1]	1	1			T144	1		-	-		-	-
all_levels[33]	auto[0]	24	1			T18	1		T47	1		T130	1
all_levels[33]	auto[1]	5	1			T230	1		T178	1		T231	1
all_levels[34]	auto[0]	20	1			T97	1		T126	1		T122	1
all_levels[34]	auto[1]	10	1			T232	5		T233	3		T234	1
all_levels[35]	auto[0]	16	1			T47	1		T131	1		T103	1
all_levels[35]	auto[1]	4	1			T235	1		T236	3		-	-
all_levels[36]	auto[0]	15	1			T132	1		T133	1		T134	2
all_levels[36]	auto[1]	2	1			T237	1		T238	1		-	-
all_levels[37]	auto[0]	14	1			T135	1		T136	1		T137	1
all_levels[38]	auto[0]	19	1			T15	1		T16	1		T26	1
all_levels[39]	auto[0]	18	1			T136	1		T138	1		T139	1
all_levels[39]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[40]	auto[0]	20	1			T11	1		T118	1		T137	1
all_levels[40]	auto[1]	3	1			T240	1		T241	2		-	-
all_levels[41]	auto[0]	15	1			T118	1		T140	1		T121	1
all_levels[41]	auto[1]	2	1			T242	2		-	-		-	-
all_levels[42]	auto[0]	14	1			T118	1		T46	1		T132	1
all_levels[42]	auto[1]	3	1			T212	1		T243	2		-	-
all_levels[43]	auto[0]	14	1			T116	1		T141	1		T129	2
all_levels[43]	auto[1]	4	1			T178	3		T244	1		-	-
all_levels[44]	auto[0]	12	1			T46	1		T142	2		T143	1
all_levels[44]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[45]	auto[0]	9	1			T98	1		T130	1		T144	1
all_levels[45]	auto[1]	4	1			T144	2		T185	2		-	-
all_levels[46]	auto[0]	9	1			T145	1		T146	1		T147	1
all_levels[46]	auto[1]	3	1			T246	2		T247	1		-	-
all_levels[47]	auto[0]	6	1			T120	1		T145	1		T148	1
all_levels[48]	auto[0]	10	1			T135	1		T122	1		T149	1
all_levels[49]	auto[0]	11	1			T124	1		T99	1		T150	1
all_levels[50]	auto[0]	9	1			T11	1		T120	2		T150	1
all_levels[50]	auto[1]	1	1			T187	1		-	-		-	-
all_levels[51]	auto[0]	9	1			T116	1		T151	2		T148	1
all_levels[52]	auto[0]	6	1			T142	1		T152	1		T153	1
all_levels[53]	auto[0]	3	1			T15	1		T134	1		T154	1
all_levels[53]	auto[1]	2	1			T15	2		-	-		-	-
all_levels[54]	auto[0]	8	1			T122	1		T155	1		T156	1
all_levels[55]	auto[0]	7	1			T11	1		T103	1		T157	1
all_levels[55]	auto[1]	7	1			T157	2		T248	2		T249	3
all_levels[56]	auto[0]	5	1			T118	1		T158	1		T159	1
all_levels[57]	auto[0]	5	1			T160	1		T26	1		T131	1
all_levels[57]	auto[1]	3	1			T131	2		T250	1		-	-
all_levels[58]	auto[0]	5	1			T17	1		T155	1		T161	1
all_levels[58]	auto[1]	2	1			T204	2		-	-		-	-
all_levels[59]	auto[0]	12	1			T162	1		T163	1		T164	1
all_levels[59]	auto[1]	3	1			T162	1		T230	1		T251	1
all_levels[60]	auto[0]	8	1			T110	1		T140	1		T141	1
all_levels[61]	auto[0]	4	1			T11	1		T47	1		T99	1
all_levels[62]	auto[0]	5	1			T41	1		T165	1		T158	1
all_levels[63]	auto[0]	7	1			T17	1		T166	1		T167	1
all_levels[63]	auto[1]	3	1			T252	3		-	-		-	-
all_levels[64]	auto[0]	78	1			T16	3		T17	1		T18	2
all_levels[64]	auto[1]	5	1			T242	1		T253	2		T224	1