Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	74724	1			T1	2		T2	2		T5	2
all_pins[1]	74724	1			T1	2		T2	2		T5	2
all_pins[2]	74724	1			T1	2		T2	2		T5	2
all_pins[3]	74724	1			T1	2		T2	2		T5	2
all_pins[4]	74724	1			T1	2		T2	2		T5	2
all_pins[5]	74724	1			T1	2		T2	2		T5	2
all_pins[6]	74724	1			T1	2		T2	2		T5	2
all_pins[7]	74724	1			T1	2		T2	2		T5	2
all_pins[8]	74724	1			T1	2		T2	2		T5	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	641691	1			T1	18		T2	18		T5	18
values[0x1]	30825	1			T6	2		T7	1		T10	6
transitions[0x0=>0x1]	24750	1			T6	1		T7	1		T10	5
transitions[0x1=>0x0]	24567	1			T6	1		T10	6		T11	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	60598	1			T1	2		T2	2		T5	2
all_pins[0]	values[0x1]	14126	1			T6	1		T7	1		T20	1
all_pins[0]	transitions[0x0=>0x1]	13678	1			T6	1		T7	1		T20	1
all_pins[0]	transitions[0x1=>0x0]	980	1			T13	1		T16	4		T18	9
all_pins[1]	values[0x0]	73296	1			T1	2		T2	2		T5	2
all_pins[1]	values[0x1]	1428	1			T13	1		T16	4		T18	9
all_pins[1]	transitions[0x0=>0x1]	1330	1			T13	1		T16	4		T18	9
all_pins[1]	transitions[0x1=>0x0]	1978	1			T10	1		T12	5		T13	3
all_pins[2]	values[0x0]	72648	1			T1	2		T2	2		T5	2
all_pins[2]	values[0x1]	2076	1			T10	1		T12	5		T13	3
all_pins[2]	transitions[0x0=>0x1]	2016	1			T10	1		T12	5		T13	3
all_pins[2]	transitions[0x1=>0x0]	193	1			T19	1		T23	2		T116	2
all_pins[3]	values[0x0]	74471	1			T1	2		T2	2		T5	2
all_pins[3]	values[0x1]	253	1			T19	1		T23	2		T116	2
all_pins[3]	transitions[0x0=>0x1]	214	1			T19	1		T23	2		T116	2
all_pins[3]	transitions[0x1=>0x0]	320	1			T13	2		T19	6		T22	6
all_pins[4]	values[0x0]	74365	1			T1	2		T2	2		T5	2
all_pins[4]	values[0x1]	359	1			T13	2		T19	6		T22	6
all_pins[4]	transitions[0x0=>0x1]	285	1			T13	1		T19	6		T22	6
all_pins[4]	transitions[0x1=>0x0]	151	1			T13	1		T23	2		T72	1
all_pins[5]	values[0x0]	74499	1			T1	2		T2	2		T5	2
all_pins[5]	values[0x1]	225	1			T13	2		T23	7		T72	1
all_pins[5]	transitions[0x0=>0x1]	169	1			T13	2		T23	7		T72	1
all_pins[5]	transitions[0x1=>0x0]	714	1			T10	2		T11	2		T16	9
all_pins[6]	values[0x0]	73954	1			T1	2		T2	2		T5	2
all_pins[6]	values[0x1]	770	1			T10	2		T11	2		T16	9
all_pins[6]	transitions[0x0=>0x1]	721	1			T10	2		T11	2		T16	9
all_pins[6]	transitions[0x1=>0x0]	226	1			T13	2		T18	2		T26	4
all_pins[7]	values[0x0]	74449	1			T1	2		T2	2		T5	2
all_pins[7]	values[0x1]	275	1			T13	2		T18	2		T26	4
all_pins[7]	transitions[0x0=>0x1]	165	1			T13	2		T18	2		T26	4
all_pins[7]	transitions[0x1=>0x0]	11203	1			T6	1		T10	3		T13	13
all_pins[8]	values[0x0]	63411	1			T1	2		T2	2		T5	2
all_pins[8]	values[0x1]	11313	1			T6	1		T10	3		T13	13
all_pins[8]	transitions[0x0=>0x1]	6172	1			T10	2		T13	9		T15	1
all_pins[8]	transitions[0x1=>0x0]	8802	1			T13	5		T16	12		T18	2