Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	4672956	1			T7	1		T10	4		T11	7
all_levels[1]	895070	1			T12	2		T13	4		T16	11
all_levels[2]	246293	1			T10	1		T12	3		T13	1
all_levels[3]	150419	1			T13	1		T16	3		T17	1
all_levels[4]	438045	1			T13	1		T43	4		T110	7
all_levels[5]	229127	1			T13	1		T16	3		T43	11
all_levels[6]	134194	1			T10	1		T13	1		T18	3
all_levels[7]	140013	1			T10	2		T13	2		T18	3
all_levels[8]	348577	1			T11	1		T13	2		T41	1
all_levels[9]	511369	1			T12	1		T13	1		T41	1
all_levels[10]	146860	1			T17	1		T41	1		T43	6
all_levels[11]	137609	1			T10	7		T43	9		T110	3
all_levels[12]	218208	1			T41	1		T43	9		T44	1
all_levels[13]	118668	1			T41	3		T43	6		T266	50
all_levels[14]	405045	1			T13	2		T18	2		T43	5
all_levels[15]	140864	1			T11	2		T17	2		T41	1
all_levels[16]	166939	1			T41	1		T18	2		T43	5
all_levels[17]	146173	1			T11	2		T13	1		T41	4
all_levels[18]	194925	1			T41	1		T43	2		T44	3
all_levels[19]	121783	1			T12	3		T13	1		T41	3
all_levels[20]	118653	1			T13	1		T41	1		T43	58
all_levels[21]	106732	1			T13	2		T43	101		T110	2
all_levels[22]	106801	1			T13	2		T41	1		T43	124
all_levels[23]	109603	1			T15	1		T260	7		T312	9
all_levels[24]	102766	1			T115	7		T260	7		T45	4
all_levels[25]	248330	1			T13	1		T41	1		T26	1
all_levels[26]	110119	1			T13	1		T26	2		T260	2
all_levels[27]	228456	1			T41	1		T26	6		T312	22
all_levels[28]	93627	1			T26	2		T45	3		T312	29
all_levels[29]	87962	1			T13	3		T266	1		T44	1
all_levels[30]	92990	1			T13	2		T41	2		T110	2
all_levels[31]	363787	1			T13	87		T266	2		T26	2
all_levels[32]	11737526	1			T11	12		T12	9		T13	769

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23066843

1

T10

14

T11

23

T12

24

auto[1]

3646

1

T7

1

T10

1

T11

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	4670924	1			T10	4		T11	7		T12	9
all_levels[0]	auto[1]	2032	1			T7	1		T12	2		T21	1
all_levels[1]	auto[0]	894827	1			T12	2		T13	4		T16	11
all_levels[1]	auto[1]	243	1			T113	1		T273	1		T318	1
all_levels[2]	auto[0]	246279	1			T10	1		T12	2		T13	1
all_levels[2]	auto[1]	14	1			T12	1		T113	1		T46	1
all_levels[3]	auto[0]	150352	1			T13	1		T16	3		T17	1
all_levels[3]	auto[1]	67	1			T261	1		T126	1		T300	3
all_levels[4]	auto[0]	438010	1			T13	1		T43	4		T110	7
all_levels[4]	auto[1]	35	1			T261	1		T267	1		T276	1
all_levels[5]	auto[0]	229091	1			T13	1		T16	3		T43	11
all_levels[5]	auto[1]	36	1			T261	1		T126	3		T300	1
all_levels[6]	auto[0]	134161	1			T10	1		T13	1		T18	3
all_levels[6]	auto[1]	33	1			T97	1		T162	1		T127	1
all_levels[7]	auto[0]	139892	1			T10	2		T13	2		T18	3
all_levels[7]	auto[1]	121	1			T291	10		T72	8		T140	1
all_levels[8]	auto[0]	348560	1			T11	1		T13	2		T41	1
all_levels[8]	auto[1]	17	1			T109	1		T175	2		T406	1
all_levels[9]	auto[0]	511349	1			T12	1		T13	1		T41	1
all_levels[9]	auto[1]	20	1			T113	2		T373	1		T407	1
all_levels[10]	auto[0]	146846	1			T17	1		T41	1		T43	6
all_levels[10]	auto[1]	14	1			T168	1		T408	1		T409	1
all_levels[11]	auto[0]	137593	1			T10	6		T43	9		T110	2
all_levels[11]	auto[1]	16	1			T10	1		T110	1		T192	1
all_levels[12]	auto[0]	218182	1			T41	1		T43	9		T44	1
all_levels[12]	auto[1]	26	1			T201	1		T132	1		T209	4
all_levels[13]	auto[0]	118648	1			T41	3		T43	6		T266	50
all_levels[13]	auto[1]	20	1			T410	1		T411	1		T412	1
all_levels[14]	auto[0]	405018	1			T13	2		T18	2		T43	5
all_levels[14]	auto[1]	27	1			T114	1		T45	1		T312	1
all_levels[15]	auto[0]	140779	1			T11	2		T17	2		T41	1
all_levels[15]	auto[1]	85	1			T124	20		T299	5		T413	23
all_levels[16]	auto[0]	166923	1			T41	1		T18	2		T43	5
all_levels[16]	auto[1]	16	1			T106	2		T144	1		T414	1
all_levels[17]	auto[0]	146139	1			T11	2		T13	1		T41	4
all_levels[17]	auto[1]	34	1			T328	1		T189	1		T209	1
all_levels[18]	auto[0]	194913	1			T41	1		T43	2		T44	3
all_levels[18]	auto[1]	12	1			T186	2		T415	1		T171	1
all_levels[19]	auto[0]	121767	1			T12	3		T13	1		T41	3
all_levels[19]	auto[1]	16	1			T416	1		T417	1		T418	1
all_levels[20]	auto[0]	118637	1			T13	1		T41	1		T43	58
all_levels[20]	auto[1]	16	1			T319	1		T264	1		T322	1
all_levels[21]	auto[0]	106710	1			T13	2		T43	101		T110	2
all_levels[21]	auto[1]	22	1			T116	1		T388	1		T263	1
all_levels[22]	auto[0]	106777	1			T13	2		T41	1		T43	124
all_levels[22]	auto[1]	24	1			T380	5		T419	1		T414	1
all_levels[23]	auto[0]	109570	1			T15	1		T260	7		T312	9
all_levels[23]	auto[1]	33	1			T124	1		T380	1		T420	1
all_levels[24]	auto[0]	102746	1			T115	7		T260	7		T45	4
all_levels[24]	auto[1]	20	1			T320	1		T421	1		T193	1
all_levels[25]	auto[0]	248310	1			T13	1		T41	1		T26	1
all_levels[25]	auto[1]	20	1			T201	2		T272	1		T129	1
all_levels[26]	auto[0]	110104	1			T13	1		T26	2		T260	2
all_levels[26]	auto[1]	15	1			T422	1		T180	3		T423	1
all_levels[27]	auto[0]	228431	1			T41	1		T26	6		T312	22
all_levels[27]	auto[1]	25	1			T412	1		T146	1		T424	1
all_levels[28]	auto[0]	93602	1			T26	2		T45	3		T312	29
all_levels[28]	auto[1]	25	1			T126	3		T120	1		T321	1
all_levels[29]	auto[0]	87947	1			T13	3		T266	1		T44	1
all_levels[29]	auto[1]	15	1			T119	2		T300	2		T195	1
all_levels[30]	auto[0]	92973	1			T13	2		T41	2		T110	2
all_levels[30]	auto[1]	17	1			T344	1		T289	2		T425	1
all_levels[31]	auto[0]	363769	1			T13	87		T266	2		T26	2
all_levels[31]	auto[1]	18	1			T157	1		T104	1		T426	1
all_levels[32]	auto[0]	11737014	1			T11	11		T12	7		T13	769
all_levels[32]	auto[1]	512	1			T11	1		T12	2		T15	3