Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	663	1			T13	4		T34	11		T37	4
all_values[1]	663	1			T13	4		T34	11		T37	4
all_values[2]	663	1			T13	4		T34	11		T37	4
all_values[3]	663	1			T13	4		T34	11		T37	4
all_values[4]	663	1			T13	4		T34	11		T37	4
all_values[5]	663	1			T13	4		T34	11		T37	4
all_values[6]	663	1			T13	4		T34	11		T37	4
all_values[7]	663	1			T13	4		T34	11		T37	4
all_values[8]	663	1			T13	4		T34	11		T37	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3093

1

T13

14

T34

50

T37

21

auto[1]

2874

1

T13

22

T34

49

T37

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2008

1

T13

10

T34

29

T37

11

auto[1]

3959

1

T13

26

T34

70

T37

25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3631

1

T13

21

T34

58

T37

22

auto[1]

2336

1

T13

15

T34

41

T37

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	225	1			T13	2		T34	5		T37	3
all_values[0]	auto[0]	auto[1]	auto[1]	190	1			T13	1		T34	4		T39	3
all_values[0]	auto[1]	auto[0]	auto[1]	135	1			T34	1		T37	1		T39	1
all_values[0]	auto[1]	auto[1]	auto[1]	113	1			T13	1		T34	1		T93	3
all_values[1]	auto[0]	auto[0]	auto[0]	204	1			T34	2		T37	2		T39	2
all_values[1]	auto[0]	auto[1]	auto[0]	200	1			T13	1		T34	3		T86	1
all_values[1]	auto[1]	auto[0]	auto[1]	128	1			T13	2		T34	3		T37	2
all_values[1]	auto[1]	auto[1]	auto[1]	131	1			T13	1		T34	3		T39	5
all_values[2]	auto[0]	auto[0]	auto[0]	129	1			T34	2		T39	3		T86	1
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T13	1		T34	2		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	117	1			T87	1		T103	2		T104	3
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T13	1		T34	2		T37	1
all_values[2]	auto[1]	auto[0]	auto[1]	145	1			T13	1		T34	3		T37	1
all_values[2]	auto[1]	auto[1]	auto[1]	117	1			T13	1		T34	2		T37	2
all_values[3]	auto[0]	auto[0]	auto[0]	168	1			T13	2		T34	5		T37	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T39	1		T93	2		T87	1
all_values[3]	auto[0]	auto[1]	auto[0]	128	1			T13	2		T34	5		T37	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T37	1		T39	1		T93	2
all_values[3]	auto[1]	auto[0]	auto[1]	132	1			T34	1		T39	3		T86	1
all_values[3]	auto[1]	auto[1]	auto[1]	112	1			T37	1		T39	1		T93	1
all_values[4]	auto[0]	auto[0]	auto[0]	145	1			T34	2		T37	3		T39	1
all_values[4]	auto[0]	auto[0]	auto[1]	60	1			T34	1		T39	2		T93	1
all_values[4]	auto[0]	auto[1]	auto[0]	129	1			T37	1		T86	3		T93	3
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T13	1		T34	1		T105	1
all_values[4]	auto[1]	auto[0]	auto[1]	140	1			T34	5		T39	3		T87	2
all_values[4]	auto[1]	auto[1]	auto[1]	123	1			T13	3		T34	2		T39	1
all_values[5]	auto[0]	auto[0]	auto[0]	136	1			T34	2		T37	1		T39	3
all_values[5]	auto[0]	auto[0]	auto[1]	64	1			T86	2		T93	2		T105	1
all_values[5]	auto[0]	auto[1]	auto[0]	112	1			T13	1		T87	3		T106	2
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T13	2		T34	2		T37	1
all_values[5]	auto[1]	auto[0]	auto[1]	125	1			T34	1		T37	2		T39	1
all_values[5]	auto[1]	auto[1]	auto[1]	143	1			T13	1		T34	6		T39	3
all_values[6]	auto[0]	auto[0]	auto[0]	141	1			T34	4		T39	3		T86	1
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T13	1		T34	1		T93	2
all_values[6]	auto[0]	auto[1]	auto[0]	121	1			T13	2		T34	3		T39	1
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T37	2		T39	1		T86	1
all_values[6]	auto[1]	auto[0]	auto[1]	122	1			T13	1		T37	1		T39	2
all_values[6]	auto[1]	auto[1]	auto[1]	141	1			T34	3		T37	1		T86	2
all_values[7]	auto[0]	auto[0]	auto[0]	144	1			T13	2		T37	2		T39	2
all_values[7]	auto[0]	auto[0]	auto[1]	54	1			T34	3		T93	2		T107	1
all_values[7]	auto[0]	auto[1]	auto[0]	134	1			T34	1		T39	5		T93	2
all_values[7]	auto[0]	auto[1]	auto[1]	66	1			T34	1		T37	1		T86	2
all_values[7]	auto[1]	auto[0]	auto[1]	129	1			T34	2		T37	1		T86	1
all_values[7]	auto[1]	auto[1]	auto[1]	136	1			T13	2		T34	4		T86	1
all_values[8]	auto[0]	auto[0]	auto[1]	216	1			T34	3		T37	1		T39	1
all_values[8]	auto[0]	auto[1]	auto[1]	183	1			T13	2		T34	4		T37	1
all_values[8]	auto[1]	auto[0]	auto[1]	146	1			T13	2		T34	2		T39	4
all_values[8]	auto[1]	auto[1]	auto[1]	118	1			T34	2		T37	2		T86	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal