Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	78151	1			T1	2		T2	2		T3	2
all_values[1]	78151	1			T1	2		T2	2		T3	2
all_values[2]	78151	1			T1	2		T2	2		T3	2
all_values[3]	78151	1			T1	2		T2	2		T3	2
all_values[4]	78151	1			T1	2		T2	2		T3	2
all_values[5]	78151	1			T1	2		T2	2		T3	2
all_values[6]	78151	1			T1	2		T2	2		T3	2
all_values[7]	78151	1			T1	2		T2	2		T3	2
all_values[8]	78151	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

355528

1

T1

18

T2

18

T3

18

auto[1]

347831

1

T4

4

T7

5

T9

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636819

1

T1

13

T2

13

T3

13

auto[1]

66540

1

T1

5

T2

5

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	21150	1			T17	12		T12	8		T106	16
all_values[0]	auto[0]	auto[1]	16237	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	23620	1			T10	1		T11	2		T17	2
all_values[0]	auto[1]	auto[1]	17144	1			T10	1		T11	4		T14	1
all_values[1]	auto[0]	auto[0]	37487	1			T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	1420	1			T107	2		T18	1		T19	13
all_values[1]	auto[1]	auto[0]	37661	1			T7	1		T10	2		T11	4
all_values[1]	auto[1]	auto[1]	1583	1			T17	3		T19	14		T21	4
all_values[2]	auto[0]	auto[0]	38546	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2226	1			T1	1		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	35241	1			T4	1		T9	10		T10	2
all_values[2]	auto[1]	auto[1]	2138	1			T11	1		T17	2		T50	1
all_values[3]	auto[0]	auto[0]	40138	1			T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	269	1			T19	2		T21	2		T132	1
all_values[3]	auto[1]	auto[0]	37520	1			T4	1		T7	1		T11	8
all_values[3]	auto[1]	auto[1]	224	1			T13	1		T18	1		T19	3
all_values[4]	auto[0]	auto[0]	36657	1			T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	299	1			T19	5		T21	3		T22	3
all_values[4]	auto[1]	auto[0]	40842	1			T4	1		T7	1		T10	2
all_values[4]	auto[1]	auto[1]	353	1			T19	8		T109	3		T28	2
all_values[5]	auto[0]	auto[0]	39040	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	161	1			T22	3		T35	7		T36	2
all_values[5]	auto[1]	auto[0]	38782	1			T7	1		T9	10		T10	2
all_values[5]	auto[1]	auto[1]	168	1			T22	3		T35	2		T36	1
all_values[6]	auto[0]	auto[0]	41486	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	150	1			T21	3		T22	2		T35	2
all_values[6]	auto[1]	auto[0]	36367	1			T4	1		T10	2		T11	4
all_values[6]	auto[1]	auto[1]	148	1			T28	1		T22	2		T35	2
all_values[7]	auto[0]	auto[0]	41402	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	332	1			T18	1		T19	10		T21	2
all_values[7]	auto[1]	auto[0]	36141	1			T7	1		T10	2		T11	2
all_values[7]	auto[1]	auto[1]	276	1			T23	2		T19	1		T28	1
all_values[8]	auto[0]	auto[0]	26518	1			T10	1		T11	2		T17	18
all_values[8]	auto[0]	auto[1]	12010	1			T1	2		T2	2		T3	2
all_values[8]	auto[1]	auto[0]	28221	1			T17	3		T106	3		T18	6
all_values[8]	auto[1]	auto[1]	11402	1			T9	10		T14	1		T16	1