Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2603

1

T1

1

T2

1

T3

1

auto[UartRx]

2603

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4526	1			T1	2		T2	2		T3	2
values[1]	41	1			T21	1		T28	1		T26	2
values[2]	50	1			T21	1		T28	1		T29	2
values[3]	51	1			T28	1		T22	1		T36	1
values[4]	52	1			T29	1		T22	2		T26	1
values[5]	63	1			T21	2		T22	1		T36	1
values[6]	72	1			T21	1		T28	1		T35	1
values[7]	55	1			T21	1		T28	1		T37	1
values[8]	66	1			T28	2		T22	1		T36	1
values[9]	75	1			T28	2		T29	1		T35	1
values[10]	100	1			T21	1		T29	1		T35	3

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2348	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	13	1			T21	1		T26	1		T398	1
auto[UartTx]	values[2]	20	1			T21	1		T29	2		T90	1
auto[UartTx]	values[3]	22	1			T28	1		T90	1		T93	1
auto[UartTx]	values[4]	17	1			T22	1		T120	1		T330	1
auto[UartTx]	values[5]	25	1			T21	1		T22	1		T120	1
auto[UartTx]	values[6]	29	1			T21	1		T38	1		T330	1
auto[UartTx]	values[7]	25	1			T28	1		T39	1		T375	2
auto[UartTx]	values[8]	22	1			T28	1		T120	1		T375	1
auto[UartTx]	values[9]	29	1			T36	1		T37	1		T39	1
auto[UartTx]	values[10]	37	1			T21	1		T35	1		T36	1
auto[UartRx]	values[0]	2178	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	28	1			T28	1		T26	1		T120	1
auto[UartRx]	values[2]	30	1			T28	1		T37	1		T38	1
auto[UartRx]	values[3]	29	1			T22	1		T36	1		T39	1
auto[UartRx]	values[4]	35	1			T29	1		T22	1		T26	1
auto[UartRx]	values[5]	38	1			T21	1		T36	1		T26	1
auto[UartRx]	values[6]	43	1			T28	1		T35	1		T36	1
auto[UartRx]	values[7]	30	1			T21	1		T37	1		T375	1
auto[UartRx]	values[8]	44	1			T28	1		T22	1		T36	1
auto[UartRx]	values[9]	46	1			T28	2		T29	1		T35	1
auto[UartRx]	values[10]	63	1			T29	1		T35	2		T36	1