Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1985	1			T4	6		T7	2		T14	10
auto[BaudRate115200]	1553	1			T1	1		T2	1		T8	1
auto[BaudRate230400]	1591	1			T3	1		T4	3		T11	2
auto[BaudRate128Kbps]	1557	1			T1	1		T9	1		T10	1
auto[BaudRate256Kbps]	1828	1			T2	1		T4	3		T8	1
auto[BaudRate1Mbps]	1401	1			T11	4		T16	6		T17	4
auto[BaudRate1p5Mbps]	1121	1			T3	1		T4	6		T10	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1056	1			T1	2		T266	2		T101	8
freqs[25]	970	1			T3	2		T11	9		T16	48
freqs[48]	555	1			T13	7		T19	3		T21	20
freqs[50]	583	1			T4	18		T49	2		T283	6
freqs[100]	1388	1			T8	2		T41	13		T42	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	196	1			T266	1		T323	1		T269	2
auto[BaudRate9600]	freqs[25]	173	1			T16	3		T30	1		T275	1
auto[BaudRate9600]	freqs[48]	118	1			T21	4		T46	4		T28	8
auto[BaudRate9600]	freqs[50]	84	1			T4	6		T98	2		T114	1
auto[BaudRate9600]	freqs[100]	228	1			T41	13		T29	2		T341	1
auto[BaudRate115200]	freqs[24]	149	1			T1	1		T101	1		T323	1
auto[BaudRate115200]	freqs[25]	140	1			T11	2		T16	12		T50	1
auto[BaudRate115200]	freqs[48]	67	1			T19	1		T21	2		T46	1
auto[BaudRate115200]	freqs[50]	88	1			T98	6		T114	2		T299	2
auto[BaudRate115200]	freqs[100]	197	1			T8	1		T288	2		T316	1
auto[BaudRate230400]	freqs[24]	147	1			T266	1		T101	2		T269	4
auto[BaudRate230400]	freqs[25]	151	1			T3	1		T11	2		T16	3
auto[BaudRate230400]	freqs[48]	59	1			T19	1		T21	4		T28	4
auto[BaudRate230400]	freqs[50]	82	1			T4	3		T283	1		T98	2
auto[BaudRate230400]	freqs[100]	196	1			T42	1		T29	1		T288	3
auto[BaudRate128Kbps]	freqs[24]	155	1			T1	1		T101	2		T323	2
auto[BaudRate128Kbps]	freqs[25]	151	1			T16	18		T30	1		T399	3
auto[BaudRate128Kbps]	freqs[48]	66	1			T19	1		T21	5		T28	2
auto[BaudRate128Kbps]	freqs[50]	78	1			T98	2		T299	2		T36	3
auto[BaudRate128Kbps]	freqs[100]	154	1			T42	1		T29	2		T288	1
auto[BaudRate256Kbps]	freqs[24]	169	1			T101	2		T323	1		T269	2
auto[BaudRate256Kbps]	freqs[25]	150	1			T11	1		T16	6		T24	1
auto[BaudRate256Kbps]	freqs[48]	70	1			T13	2		T21	1		T46	1
auto[BaudRate256Kbps]	freqs[50]	96	1			T4	3		T98	4		T114	2
auto[BaudRate256Kbps]	freqs[100]	208	1			T8	1		T395	1		T29	1
auto[BaudRate1Mbps]	freqs[24]	149	1			T101	1		T323	1		T269	3
auto[BaudRate1Mbps]	freqs[25]	128	1			T11	4		T16	6		T111	2
auto[BaudRate1Mbps]	freqs[48]	91	1			T13	3		T21	2		T46	2
auto[BaudRate1Mbps]	freqs[50]	74	1			T283	2		T98	2		T114	2
auto[BaudRate1Mbps]	freqs[100]	199	1			T288	1		T365	1		T316	4
auto[BaudRate1p5Mbps]	freqs[25]	77	1			T3	1		T275	1		T22	2
auto[BaudRate1p5Mbps]	freqs[48]	84	1			T13	2		T21	2		T28	3
auto[BaudRate1p5Mbps]	freqs[50]	81	1			T4	6		T49	2		T283	3
auto[BaudRate1p5Mbps]	freqs[100]	206	1			T288	1		T365	1		T316	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded