Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	22352840	1			T4	2		T7	1		T9	9
all_levels[1]	139107	1			T10	1		T11	2		T17	2
all_levels[2]	2154	1			T17	2		T106	5		T46	1
all_levels[3]	983	1			T11	1		T17	1		T106	1
all_levels[4]	668	1			T17	1		T12	1		T50	1
all_levels[5]	478	1			T11	2		T12	1		T106	4
all_levels[6]	403	1			T11	1		T17	1		T12	1
all_levels[7]	347	1			T17	1		T13	2		T18	1
all_levels[8]	267	1			T11	1		T17	1		T12	1
all_levels[9]	250	1			T11	1		T107	1		T123	2
all_levels[10]	163	1			T114	2		T55	1		T124	1
all_levels[11]	163	1			T11	1		T50	2		T13	1
all_levels[12]	150	1			T11	2		T40	1		T47	1
all_levels[13]	129	1			T123	1		T114	1		T125	1
all_levels[14]	120	1			T101	1		T89	1		T126	1
all_levels[15]	98	1			T101	2		T55	1		T127	1
all_levels[16]	114	1			T13	1		T114	1		T127	1
all_levels[17]	101	1			T11	2		T12	1		T18	1
all_levels[18]	81	1			T106	2		T128	1		T124	1
all_levels[19]	79	1			T107	1		T128	1		T114	1
all_levels[20]	77	1			T129	2		T130	1		T131	2
all_levels[21]	51	1			T18	1		T132	1		T133	1
all_levels[22]	55	1			T11	1		T124	1		T134	1
all_levels[23]	57	1			T135	1		T136	1		T137	1
all_levels[24]	41	1			T135	1		T138	1		T139	2
all_levels[25]	52	1			T140	1		T127	1		T141	1
all_levels[26]	57	1			T107	1		T18	1		T40	1
all_levels[27]	49	1			T128	2		T142	1		T135	1
all_levels[28]	30	1			T11	1		T106	1		T136	1
all_levels[29]	35	1			T12	2		T18	1		T128	1
all_levels[30]	41	1			T128	1		T111	1		T129	1
all_levels[31]	35	1			T142	1		T143	1		T144	1
all_levels[32]	22	1			T35	1		T145	1		T146	1
all_levels[33]	25	1			T128	1		T114	1		T124	1
all_levels[34]	25	1			T12	1		T130	1		T147	1
all_levels[35]	31	1			T110	1		T148	1		T149	1
all_levels[36]	16	1			T135	1		T114	1		T150	1
all_levels[37]	26	1			T101	1		T135	4		T124	1
all_levels[38]	25	1			T110	1		T151	1		T152	1
all_levels[39]	15	1			T153	1		T154	1		T151	1
all_levels[40]	18	1			T111	1		T134	1		T141	1
all_levels[41]	12	1			T128	1		T155	1		T156	1
all_levels[42]	13	1			T101	1		T125	1		T143	1
all_levels[43]	16	1			T110	1		T157	1		T144	1
all_levels[44]	6	1			T158	1		T159	1		T160	2
all_levels[45]	13	1			T138	1		T144	2		T161	1
all_levels[46]	18	1			T12	1		T162	1		T163	1
all_levels[47]	7	1			T103	1		T164	1		T165	1
all_levels[48]	11	1			T157	1		T166	1		T167	1
all_levels[49]	12	1			T168	3		T147	1		T169	1
all_levels[50]	9	1			T143	1		T170	1		T171	1
all_levels[51]	8	1			T172	2		T165	1		T173	1
all_levels[52]	10	1			T157	1		T143	1		T174	1
all_levels[53]	8	1			T175	1		T176	1		T170	1
all_levels[54]	6	1			T177	2		T178	1		T179	1
all_levels[55]	14	1			T128	1		T177	1		T143	1
all_levels[56]	5	1			T103	2		T167	1		T180	1
all_levels[57]	7	1			T143	1		T167	1		T181	1
all_levels[58]	4	1			T157	1		T182	1		T183	2
all_levels[59]	5	1			T12	1		T157	1		T184	1
all_levels[60]	7	1			T134	1		T170	1		T185	1
all_levels[61]	5	1			T128	1		T143	1		T156	1
all_levels[62]	2	1			T186	1		T164	1		-	-
all_levels[63]	9	1			T134	1		T175	1		T133	1
all_levels[64]	78	1			T13	1		T18	1		T132	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22496147

1

T10

18

T11

52

T17

159

auto[1]

3616

1

T4

2

T7

1

T9

9

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	22349646	1			T10	17		T11	37		T17	150
all_levels[0]	auto[1]	3194	1			T4	2		T7	1		T9	9
all_levels[1]	auto[0]	139034	1			T10	1		T11	2		T17	2
all_levels[1]	auto[1]	73	1			T106	2		T114	1		T187	2
all_levels[2]	auto[0]	2128	1			T17	2		T106	5		T46	1
all_levels[2]	auto[1]	26	1			T188	2		T189	1		T190	1
all_levels[3]	auto[0]	967	1			T11	1		T17	1		T106	1
all_levels[3]	auto[1]	16	1			T191	1		T192	1		T193	3
all_levels[4]	auto[0]	648	1			T17	1		T12	1		T50	1
all_levels[4]	auto[1]	20	1			T150	2		T155	3		T194	1
all_levels[5]	auto[0]	461	1			T11	2		T12	1		T106	4
all_levels[5]	auto[1]	17	1			T195	5		T196	1		T197	2
all_levels[6]	auto[0]	382	1			T11	1		T17	1		T12	1
all_levels[6]	auto[1]	21	1			T198	1		T199	1		T200	1
all_levels[7]	auto[0]	321	1			T17	1		T13	2		T18	1
all_levels[7]	auto[1]	26	1			T201	2		T189	1		T202	2
all_levels[8]	auto[0]	252	1			T11	1		T17	1		T12	1
all_levels[8]	auto[1]	15	1			T136	1		T114	1		T203	2
all_levels[9]	auto[0]	229	1			T11	1		T107	1		T123	2
all_levels[9]	auto[1]	21	1			T201	1		T195	1		T204	1
all_levels[10]	auto[0]	158	1			T114	2		T55	1		T124	1
all_levels[10]	auto[1]	5	1			T174	1		T205	2		T206	1
all_levels[11]	auto[0]	155	1			T11	1		T50	2		T13	1
all_levels[11]	auto[1]	8	1			T184	1		T207	1		T208	1
all_levels[12]	auto[0]	145	1			T11	2		T40	1		T47	1
all_levels[12]	auto[1]	5	1			T209	1		T210	1		T211	1
all_levels[13]	auto[0]	125	1			T123	1		T114	1		T125	1
all_levels[13]	auto[1]	4	1			T146	1		T212	1		T213	1
all_levels[14]	auto[0]	118	1			T101	1		T89	1		T126	1
all_levels[14]	auto[1]	2	1			T150	1		T214	1		-	-
all_levels[15]	auto[0]	94	1			T101	2		T55	1		T127	1
all_levels[15]	auto[1]	4	1			T215	1		T216	1		T217	1
all_levels[16]	auto[0]	100	1			T13	1		T114	1		T127	1
all_levels[16]	auto[1]	14	1			T145	1		T159	2		T172	1
all_levels[17]	auto[0]	91	1			T11	2		T12	1		T18	1
all_levels[17]	auto[1]	10	1			T114	2		T218	1		T219	1
all_levels[18]	auto[0]	73	1			T106	1		T128	1		T124	1
all_levels[18]	auto[1]	8	1			T106	1		T148	1		T220	1
all_levels[19]	auto[0]	76	1			T107	1		T128	1		T114	1
all_levels[19]	auto[1]	3	1			T177	1		T221	1		T222	1
all_levels[20]	auto[0]	64	1			T129	2		T130	1		T131	2
all_levels[20]	auto[1]	13	1			T187	2		T211	2		T223	3
all_levels[21]	auto[0]	45	1			T18	1		T132	1		T133	1
all_levels[21]	auto[1]	6	1			T224	1		T225	2		T226	3
all_levels[22]	auto[0]	52	1			T11	1		T124	1		T134	1
all_levels[22]	auto[1]	3	1			T227	1		T228	1		T229	1
all_levels[23]	auto[0]	51	1			T135	1		T136	1		T137	1
all_levels[23]	auto[1]	6	1			T230	1		T210	2		T231	1
all_levels[24]	auto[0]	40	1			T135	1		T138	1		T139	2
all_levels[24]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[25]	auto[0]	44	1			T140	1		T127	1		T141	1
all_levels[25]	auto[1]	8	1			T233	2		T234	2		T235	2
all_levels[26]	auto[0]	51	1			T107	1		T18	1		T40	1
all_levels[26]	auto[1]	6	1			T192	1		T236	2		T237	1
all_levels[27]	auto[0]	38	1			T128	2		T142	1		T135	1
all_levels[27]	auto[1]	11	1			T194	1		T238	6		T239	2
all_levels[28]	auto[0]	25	1			T11	1		T106	1		T136	1
all_levels[28]	auto[1]	5	1			T240	2		T241	1		T242	2
all_levels[29]	auto[0]	30	1			T12	2		T18	1		T128	1
all_levels[29]	auto[1]	5	1			T243	1		T244	4		-	-
all_levels[30]	auto[0]	35	1			T128	1		T111	1		T129	1
all_levels[30]	auto[1]	6	1			T209	1		T245	1		T246	1
all_levels[31]	auto[0]	31	1			T142	1		T143	1		T144	1
all_levels[31]	auto[1]	4	1			T247	1		T207	1		T248	2
all_levels[32]	auto[0]	20	1			T35	1		T145	1		T146	1
all_levels[32]	auto[1]	2	1			T249	1		T250	1		-	-
all_levels[33]	auto[0]	24	1			T128	1		T114	1		T124	1
all_levels[33]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[34]	auto[0]	21	1			T12	1		T130	1		T147	1
all_levels[34]	auto[1]	4	1			T189	4		-	-		-	-
all_levels[35]	auto[0]	29	1			T110	1		T148	1		T149	1
all_levels[35]	auto[1]	2	1			T251	2		-	-		-	-
all_levels[36]	auto[0]	15	1			T135	1		T114	1		T150	1
all_levels[36]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[37]	auto[0]	23	1			T101	1		T135	1		T124	1
all_levels[37]	auto[1]	3	1			T135	3		-	-		-	-
all_levels[38]	auto[0]	22	1			T110	1		T151	1		T152	1
all_levels[38]	auto[1]	3	1			T144	2		T253	1		-	-
all_levels[39]	auto[0]	15	1			T153	1		T154	1		T151	1
all_levels[40]	auto[0]	17	1			T111	1		T134	1		T141	1
all_levels[40]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[41]	auto[0]	11	1			T128	1		T155	1		T156	1
all_levels[41]	auto[1]	1	1			T255	1		-	-		-	-
all_levels[42]	auto[0]	13	1			T101	1		T125	1		T143	1
all_levels[43]	auto[0]	15	1			T110	1		T157	1		T144	1
all_levels[43]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[44]	auto[0]	5	1			T158	1		T159	1		T160	1
all_levels[44]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[45]	auto[0]	9	1			T138	1		T144	1		T161	1
all_levels[45]	auto[1]	4	1			T144	1		T257	1		T227	2
all_levels[46]	auto[0]	15	1			T12	1		T162	1		T163	1
all_levels[46]	auto[1]	3	1			T258	1		T231	2		-	-
all_levels[47]	auto[0]	7	1			T103	1		T164	1		T165	1
all_levels[48]	auto[0]	9	1			T157	1		T166	1		T167	1
all_levels[48]	auto[1]	2	1			T259	2		-	-		-	-
all_levels[49]	auto[0]	10	1			T168	1		T147	1		T169	1
all_levels[49]	auto[1]	2	1			T168	2		-	-		-	-
all_levels[50]	auto[0]	8	1			T143	1		T170	1		T171	1
all_levels[50]	auto[1]	1	1			T260	1		-	-		-	-
all_levels[51]	auto[0]	7	1			T172	1		T165	1		T173	1
all_levels[51]	auto[1]	1	1			T172	1		-	-		-	-
all_levels[52]	auto[0]	8	1			T157	1		T143	1		T174	1
all_levels[52]	auto[1]	2	1			T261	1		T183	1		-	-
all_levels[53]	auto[0]	7	1			T175	1		T176	1		T170	1
all_levels[53]	auto[1]	1	1			T262	1		-	-		-	-
all_levels[54]	auto[0]	5	1			T177	1		T178	1		T179	1
all_levels[54]	auto[1]	1	1			T177	1		-	-		-	-
all_levels[55]	auto[0]	10	1			T128	1		T177	1		T143	1
all_levels[55]	auto[1]	4	1			T226	1		T263	3		-	-
all_levels[56]	auto[0]	4	1			T103	1		T167	1		T180	1
all_levels[56]	auto[1]	1	1			T103	1		-	-		-	-
all_levels[57]	auto[0]	7	1			T143	1		T167	1		T181	1
all_levels[58]	auto[0]	3	1			T157	1		T182	1		T183	1
all_levels[58]	auto[1]	1	1			T183	1		-	-		-	-
all_levels[59]	auto[0]	5	1			T12	1		T157	1		T184	1
all_levels[60]	auto[0]	6	1			T134	1		T170	1		T185	1
all_levels[60]	auto[1]	1	1			T264	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T128	1		T143	1		T156	1
all_levels[62]	auto[0]	2	1			T186	1		T164	1		-	-
all_levels[63]	auto[0]	8	1			T134	1		T175	1		T133	1
all_levels[63]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[64]	auto[0]	73	1			T13	1		T18	1		T132	1
all_levels[64]	auto[1]	5	1			T219	1		T243	2		T265	1