Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	78151	1			T1	2		T2	2		T3	2
all_pins[1]	78151	1			T1	2		T2	2		T3	2
all_pins[2]	78151	1			T1	2		T2	2		T3	2
all_pins[3]	78151	1			T1	2		T2	2		T3	2
all_pins[4]	78151	1			T1	2		T2	2		T3	2
all_pins[5]	78151	1			T1	2		T2	2		T3	2
all_pins[6]	78151	1			T1	2		T2	2		T3	2
all_pins[7]	78151	1			T1	2		T2	2		T3	2
all_pins[8]	78151	1			T1	2		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	669148	1			T1	18		T2	18		T3	18
values[0x1]	34211	1			T9	10		T10	1		T11	5
transitions[0x0=>0x1]	26383	1			T9	9		T10	1		T11	5
transitions[0x1=>0x0]	26165	1			T9	10		T11	5		T14	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	60950	1			T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	17201	1			T10	1		T11	4		T14	1
all_pins[0]	transitions[0x0=>0x1]	16720	1			T10	1		T11	4		T14	1
all_pins[0]	transitions[0x1=>0x0]	1097	1			T17	3		T19	14		T21	2
all_pins[1]	values[0x0]	76573	1			T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1578	1			T17	3		T19	14		T21	4
all_pins[1]	transitions[0x0=>0x1]	1455	1			T17	1		T19	14		T21	3
all_pins[1]	transitions[0x1=>0x0]	2045	1			T11	1		T50	1		T13	1
all_pins[2]	values[0x0]	75983	1			T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	2168	1			T11	1		T17	2		T50	1
all_pins[2]	transitions[0x0=>0x1]	2119	1			T11	1		T17	2		T50	1
all_pins[2]	transitions[0x1=>0x0]	175	1			T13	1		T18	1		T19	3
all_pins[3]	values[0x0]	77927	1			T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	224	1			T13	1		T18	1		T19	3
all_pins[3]	transitions[0x0=>0x1]	184	1			T13	1		T18	1		T19	3
all_pins[3]	transitions[0x1=>0x0]	313	1			T19	8		T109	3		T28	2
all_pins[4]	values[0x0]	77798	1			T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	353	1			T19	8		T109	3		T28	2
all_pins[4]	transitions[0x0=>0x1]	291	1			T19	8		T109	3		T28	2
all_pins[4]	transitions[0x1=>0x0]	137	1			T22	1		T25	1		T35	1
all_pins[5]	values[0x0]	77952	1			T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	199	1			T22	3		T25	1		T35	2
all_pins[5]	transitions[0x0=>0x1]	151	1			T22	2		T25	1		T35	2
all_pins[5]	transitions[0x1=>0x0]	722	1			T17	2		T12	1		T13	1
all_pins[6]	values[0x0]	77381	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	770	1			T17	2		T12	1		T13	1
all_pins[6]	transitions[0x0=>0x1]	721	1			T17	2		T12	1		T13	1
all_pins[6]	transitions[0x1=>0x0]	227	1			T23	2		T19	1		T28	1
all_pins[7]	values[0x0]	77875	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	276	1			T23	2		T19	1		T28	1
all_pins[7]	transitions[0x0=>0x1]	177	1			T23	2		T19	1		T128	3
all_pins[7]	transitions[0x1=>0x0]	11343	1			T9	10		T14	1		T16	1
all_pins[8]	values[0x0]	66709	1			T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	11442	1			T9	10		T14	1		T16	1
all_pins[8]	transitions[0x0=>0x1]	4565	1			T9	9		T50	2		T13	1
all_pins[8]	transitions[0x1=>0x0]	10106	1			T11	4		T17	7		T106	3