Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	4549067	1			T7	1		T9	9		T11	5
all_levels[1]	1769857	1			T11	8		T17	105		T12	2
all_levels[2]	570613	1			T11	2		T12	2		T50	2
all_levels[3]	167529	1			T12	1		T107	2		T48	4
all_levels[4]	247567	1			T11	3		T17	3		T50	1
all_levels[5]	170769	1			T11	2		T50	2		T13	1
all_levels[6]	554340	1			T11	2		T12	1		T50	3
all_levels[7]	253317	1			T11	2		T13	2		T106	4
all_levels[8]	409125	1			T17	8		T13	1		T106	1
all_levels[9]	283683	1			T12	1		T13	1		T106	4
all_levels[10]	140286	1			T13	1		T106	2		T48	10
all_levels[11]	159028	1			T106	2		T40	2		T48	3
all_levels[12]	302183	1			T10	4		T17	5		T106	2
all_levels[13]	154945	1			T10	8		T106	3		T21	1
all_levels[14]	143858	1			T106	2		T18	3		T28	82
all_levels[15]	157078	1			T10	1		T12	1		T18	2
all_levels[16]	258263	1			T13	2		T106	2		T107	2
all_levels[17]	155235	1			T12	3		T18	1		T21	2
all_levels[18]	139501	1			T21	1		T28	5		T52	261
all_levels[19]	150728	1			T10	1		T18	2		T28	4
all_levels[20]	480694	1			T18	1		T21	2		T48	1
all_levels[21]	148576	1			T10	5		T106	2		T18	3
all_levels[22]	142274	1			T106	1		T21	2		T28	4
all_levels[23]	273367	1			T18	3		T21	1		T46	143
all_levels[24]	241440	1			T21	4		T46	4		T48	2
all_levels[25]	128113	1			T13	1		T21	1		T28	4
all_levels[26]	198185	1			T12	4		T106	1		T18	1
all_levels[27]	121237	1			T21	1		T28	17		T98	7
all_levels[28]	130570	1			T106	2		T107	2		T23	3
all_levels[29]	161893	1			T106	1		T107	3		T21	1
all_levels[30]	135945	1			T107	2		T21	1		T46	1
all_levels[31]	525111	1			T13	2		T106	1		T21	45
all_levels[32]	9075278	1			T11	28		T12	10		T13	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22496147

1

T10

18

T11

52

T17

159

auto[1]

3508

1

T7

1

T9

9

T10

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	4547223	1			T11	5		T17	38		T12	10
all_levels[0]	auto[1]	1844	1			T7	1		T9	9		T106	6
all_levels[1]	auto[0]	1769632	1			T11	8		T17	105		T12	2
all_levels[1]	auto[1]	225	1			T395	1		T128	1		T136	1
all_levels[2]	auto[0]	570569	1			T11	2		T12	2		T50	2
all_levels[2]	auto[1]	44	1			T150	1		T103	3		T355	2
all_levels[3]	auto[0]	167362	1			T12	1		T107	2		T48	4
all_levels[3]	auto[1]	167	1			T25	8		T392	1		T136	1
all_levels[4]	auto[0]	247546	1			T11	3		T17	3		T50	1
all_levels[4]	auto[1]	21	1			T145	1		T403	1		T404	1
all_levels[5]	auto[0]	170749	1			T11	2		T50	2		T13	1
all_levels[5]	auto[1]	20	1			T47	1		T150	1		T405	1
all_levels[6]	auto[0]	554317	1			T11	2		T12	1		T50	3
all_levels[6]	auto[1]	23	1			T406	1		T407	1		T408	1
all_levels[7]	auto[0]	253180	1			T11	2		T13	2		T106	4
all_levels[7]	auto[1]	137	1			T19	8		T47	2		T284	1
all_levels[8]	auto[0]	409100	1			T17	8		T13	1		T106	1
all_levels[8]	auto[1]	25	1			T306	1		T145	1		T189	1
all_levels[9]	auto[0]	283646	1			T12	1		T13	1		T106	4
all_levels[9]	auto[1]	37	1			T150	1		T103	1		T409	5
all_levels[10]	auto[0]	140268	1			T13	1		T106	2		T48	10
all_levels[10]	auto[1]	18	1			T167	1		T410	1		T411	1
all_levels[11]	auto[0]	159008	1			T106	2		T40	2		T48	3
all_levels[11]	auto[1]	20	1			T267	1		T102	1		T412	1
all_levels[12]	auto[0]	302149	1			T10	4		T17	5		T106	2
all_levels[12]	auto[1]	34	1			T331	1		T329	1		T305	1
all_levels[13]	auto[0]	154920	1			T10	8		T106	3		T21	1
all_levels[13]	auto[1]	25	1			T315	1		T298	1		T195	1
all_levels[14]	auto[0]	143842	1			T106	2		T18	3		T28	82
all_levels[14]	auto[1]	16	1			T317	1		T309	1		T189	1
all_levels[15]	auto[0]	157031	1			T10	1		T12	1		T18	2
all_levels[15]	auto[1]	47	1			T48	1		T383	1		T188	1
all_levels[16]	auto[0]	258239	1			T13	2		T106	2		T107	2
all_levels[16]	auto[1]	24	1			T368	1		T367	1		T413	1
all_levels[17]	auto[0]	155219	1			T12	3		T18	1		T21	2
all_levels[17]	auto[1]	16	1			T323	2		T145	2		T414	1
all_levels[18]	auto[0]	139484	1			T21	1		T28	5		T52	261
all_levels[18]	auto[1]	17	1			T304	1		T415	1		T416	1
all_levels[19]	auto[0]	150710	1			T10	1		T18	2		T28	4
all_levels[19]	auto[1]	18	1			T201	2		T417	1		T172	2
all_levels[20]	auto[0]	480674	1			T18	1		T21	2		T48	1
all_levels[20]	auto[1]	20	1			T418	1		T419	1		T420	1
all_levels[21]	auto[0]	148552	1			T10	4		T106	2		T18	3
all_levels[21]	auto[1]	24	1			T10	1		T114	1		T148	1
all_levels[22]	auto[0]	142250	1			T106	1		T21	2		T28	4
all_levels[22]	auto[1]	24	1			T299	1		T285	1		T421	1
all_levels[23]	auto[0]	273343	1			T18	3		T21	1		T46	143
all_levels[23]	auto[1]	24	1			T422	1		T423	1		T424	3
all_levels[24]	auto[0]	241414	1			T21	4		T46	4		T48	2
all_levels[24]	auto[1]	26	1			T105	1		T425	1		T426	1
all_levels[25]	auto[0]	128085	1			T13	1		T21	1		T28	4
all_levels[25]	auto[1]	28	1			T135	3		T156	1		T355	2
all_levels[26]	auto[0]	198163	1			T12	3		T106	1		T18	1
all_levels[26]	auto[1]	22	1			T12	1		T281	1		T201	1
all_levels[27]	auto[0]	121230	1			T21	1		T28	17		T98	7
all_levels[27]	auto[1]	7	1			T187	3		T427	1		T428	2
all_levels[28]	auto[0]	130555	1			T106	2		T107	2		T23	3
all_levels[28]	auto[1]	15	1			T288	1		T168	1		T139	1
all_levels[29]	auto[0]	161878	1			T106	1		T107	3		T21	1
all_levels[29]	auto[1]	15	1			T175	1		T174	1		T213	3
all_levels[30]	auto[0]	135932	1			T107	2		T21	1		T46	1
all_levels[30]	auto[1]	13	1			T155	3		T184	1		T218	1
all_levels[31]	auto[0]	525088	1			T13	2		T106	1		T21	45
all_levels[31]	auto[1]	23	1			T172	1		T429	1		T204	1
all_levels[32]	auto[0]	9074789	1			T11	28		T12	10		T13	2
all_levels[32]	auto[1]	489	1			T107	1		T23	1		T40	1