Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	715	1			T21	8		T28	4		T22	7
all_values[1]	715	1			T21	8		T28	4		T22	7
all_values[2]	715	1			T21	8		T28	4		T22	7
all_values[3]	715	1			T21	8		T28	4		T22	7
all_values[4]	715	1			T21	8		T28	4		T22	7
all_values[5]	715	1			T21	8		T28	4		T22	7
all_values[6]	715	1			T21	8		T28	4		T22	7
all_values[7]	715	1			T21	8		T28	4		T22	7
all_values[8]	715	1			T21	8		T28	4		T22	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3514

1

T21

42

T28

20

T22

39

auto[1]

2921

1

T21

30

T28

16

T22

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2100

1

T21

31

T28

19

T22

16

auto[1]

4335

1

T21

41

T28

17

T22

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3774

1

T21

47

T28

27

T22

30

auto[1]

2661

1

T21

25

T28

9

T22

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	224	1			T21	3		T22	5		T35	6
all_values[0]	auto[0]	auto[1]	auto[1]	178	1			T21	2		T28	3		T35	2
all_values[0]	auto[1]	auto[0]	auto[1]	181	1			T21	3		T28	1		T22	2
all_values[0]	auto[1]	auto[1]	auto[1]	132	1			T35	3		T36	1		T26	3
all_values[1]	auto[0]	auto[0]	auto[0]	218	1			T21	1		T28	1		T22	2
all_values[1]	auto[0]	auto[1]	auto[0]	208	1			T21	3		T28	2		T22	2
all_values[1]	auto[1]	auto[0]	auto[1]	136	1			T21	1		T28	1		T22	1
all_values[1]	auto[1]	auto[1]	auto[1]	153	1			T21	3		T22	2		T35	2
all_values[2]	auto[0]	auto[0]	auto[0]	139	1			T28	2		T22	1		T35	1
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T21	1		T35	3		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	127	1			T21	2		T28	1		T35	2
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T21	2		T22	1		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	186	1			T21	2		T22	2		T35	3
all_values[2]	auto[1]	auto[1]	auto[1]	122	1			T21	1		T28	1		T22	3
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T21	1		T28	1		T35	4
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T22	1		T35	1		T36	1
all_values[3]	auto[0]	auto[1]	auto[0]	129	1			T21	4		T28	3		T35	4
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T36	1		T38	1		T120	1
all_values[3]	auto[1]	auto[0]	auto[1]	167	1			T21	2		T22	2		T35	6
all_values[3]	auto[1]	auto[1]	auto[1]	113	1			T21	1		T22	4		T36	3
all_values[4]	auto[0]	auto[0]	auto[0]	155	1			T21	1		T28	2		T22	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1			T21	1		T22	2		T120	1
all_values[4]	auto[0]	auto[1]	auto[0]	131	1			T21	3		T35	2		T26	3
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T28	1		T35	2		T36	2
all_values[4]	auto[1]	auto[0]	auto[1]	147	1			T21	2		T22	4		T35	2
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T21	1		T28	1		T35	4
all_values[5]	auto[0]	auto[0]	auto[0]	146	1			T21	3		T28	2		T36	2
all_values[5]	auto[0]	auto[0]	auto[1]	64	1			T22	1		T35	3		T36	1
all_values[5]	auto[0]	auto[1]	auto[0]	121	1			T21	4		T28	2		T35	2
all_values[5]	auto[0]	auto[1]	auto[1]	73	1			T35	2		T36	1		T26	1
all_values[5]	auto[1]	auto[0]	auto[1]	159	1			T22	4		T35	6		T36	2
all_values[5]	auto[1]	auto[1]	auto[1]	152	1			T21	1		T22	2		T35	2
all_values[6]	auto[0]	auto[0]	auto[0]	169	1			T21	4		T28	1		T35	5
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T21	2		T22	1		T36	1
all_values[6]	auto[0]	auto[1]	auto[0]	125	1			T28	1		T22	3		T35	3
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T22	1		T35	2		T26	1
all_values[6]	auto[1]	auto[0]	auto[1]	171	1			T21	2		T28	2		T22	1
all_values[6]	auto[1]	auto[1]	auto[1]	115	1			T22	1		T35	2		T36	2
all_values[7]	auto[0]	auto[0]	auto[0]	159	1			T21	4		T28	1		T22	4
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T21	1		T28	1		T35	3
all_values[7]	auto[0]	auto[1]	auto[0]	112	1			T21	1		T22	3		T35	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T35	1		T36	3		T120	1
all_values[7]	auto[1]	auto[0]	auto[1]	169	1			T21	2		T28	2		T35	7
all_values[7]	auto[1]	auto[1]	auto[1]	124	1			T35	2		T36	1		T26	1
all_values[8]	auto[0]	auto[0]	auto[1]	244	1			T21	4		T28	2		T22	1
all_values[8]	auto[0]	auto[1]	auto[1]	177	1			T28	1		T22	1		T35	4
all_values[8]	auto[1]	auto[0]	auto[1]	173	1			T21	2		T28	1		T22	4
all_values[8]	auto[1]	auto[1]	auto[1]	121	1			T21	2		T22	1		T35	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal