Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83665	1			T1	2		T2	2		T3	1
all_values[1]	83665	1			T1	2		T2	2		T3	1
all_values[2]	83665	1			T1	2		T2	2		T3	1
all_values[3]	83665	1			T1	2		T2	2		T3	1
all_values[4]	83665	1			T1	2		T2	2		T3	1
all_values[5]	83665	1			T1	2		T2	2		T3	1
all_values[6]	83665	1			T1	2		T2	2		T3	1
all_values[7]	83665	1			T1	2		T2	2		T3	1
all_values[8]	83665	1			T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

375166

1

T1

18

T2

18

T3

4

auto[1]

377819

1

T3

5

T5

105

T8

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674057

1

T1

13

T2

13

T3

7

auto[1]

78928

1

T1

5

T2

5

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	22227	1			T11	7		T12	10		T13	7
all_values[0]	auto[0]	auto[1]	19711	1			T1	2		T2	2		T5	21
all_values[0]	auto[1]	auto[0]	21628	1			T26	1		T20	5		T89	27
all_values[0]	auto[1]	auto[1]	20099	1			T3	1		T9	5		T11	1
all_values[1]	auto[0]	auto[0]	41681	1			T1	2		T2	2		T5	21
all_values[1]	auto[0]	auto[1]	1499	1			T9	2		T26	2		T20	1
all_values[1]	auto[1]	auto[0]	38999	1			T3	1		T9	1		T11	6
all_values[1]	auto[1]	auto[1]	1486	1			T9	3		T21	3		T12	4
all_values[2]	auto[0]	auto[0]	37031	1			T1	1		T2	1		T7	1
all_values[2]	auto[0]	auto[1]	2206	1			T1	1		T2	1		T7	1
all_values[2]	auto[1]	auto[0]	42299	1			T3	1		T5	21		T9	2
all_values[2]	auto[1]	auto[1]	2129	1			T9	3		T13	3		T86	1
all_values[3]	auto[0]	auto[0]	43074	1			T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	288	1			T20	4		T17	1		T18	3
all_values[3]	auto[1]	auto[0]	40051	1			T9	6		T11	7		T21	5
all_values[3]	auto[1]	auto[1]	252	1			T9	1		T20	2		T19	1
all_values[4]	auto[0]	auto[0]	43023	1			T1	2		T2	2		T3	1
all_values[4]	auto[0]	auto[1]	324	1			T22	6		T23	4		T17	17
all_values[4]	auto[1]	auto[0]	39942	1			T5	21		T9	2		T11	6
all_values[4]	auto[1]	auto[1]	376	1			T9	1		T21	4		T20	3
all_values[5]	auto[0]	auto[0]	38603	1			T1	2		T2	2		T5	21
all_values[5]	auto[0]	auto[1]	112	1			T37	2		T38	1		T39	1
all_values[5]	auto[1]	auto[0]	44800	1			T3	1		T9	5		T11	6
all_values[5]	auto[1]	auto[1]	150	1			T20	1		T38	2		T96	3
all_values[6]	auto[0]	auto[0]	40397	1			T1	2		T2	2		T7	2
all_values[6]	auto[0]	auto[1]	160	1			T9	4		T20	1		T39	2
all_values[6]	auto[1]	auto[0]	42937	1			T3	1		T5	21		T8	1
all_values[6]	auto[1]	auto[1]	171	1			T9	2		T20	1		T35	3
all_values[7]	auto[0]	auto[0]	41800	1			T1	2		T2	2		T3	1
all_values[7]	auto[0]	auto[1]	310	1			T9	2		T22	2		T23	1
all_values[7]	auto[1]	auto[0]	41247	1			T5	21		T9	2		T11	8
all_values[7]	auto[1]	auto[1]	308	1			T9	1		T20	3		T112	1
all_values[8]	auto[0]	auto[0]	28658	1			T11	6		T12	7		T13	2
all_values[8]	auto[0]	auto[1]	14062	1			T1	2		T2	2		T3	1
all_values[8]	auto[1]	auto[0]	25660	1			T11	1		T12	5		T13	5
all_values[8]	auto[1]	auto[1]	15285	1			T5	21		T8	1		T9	6