Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total tests in report: 1313
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
78.78 78.78 97.29 97.29 88.35 88.35 89.14 89.14 92.13 92.13 96.14 96.14 9.62 9.62 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.849997556
82.13 3.35 98.19 0.90 90.82 2.47 97.22 8.08 95.14 3.01 96.44 0.30 14.95 5.33 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_reset.4235698529
84.83 2.71 98.49 0.30 92.24 1.41 97.47 0.25 96.06 0.93 96.44 0.00 28.29 13.34 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_stress_all.2680015922
86.99 2.16 98.49 0.00 92.24 0.00 97.47 0.00 96.06 0.00 96.44 0.00 41.23 12.94 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.1711352690
88.41 1.42 98.49 0.00 92.24 0.00 97.47 0.00 96.06 0.00 96.44 0.00 49.76 8.53 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_stress_all.3412482512
89.64 1.23 98.69 0.20 93.18 0.94 97.47 0.00 96.76 0.69 97.63 1.19 54.12 4.36 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.4008658435
90.62 0.97 98.69 0.00 93.18 0.00 97.47 0.00 96.76 0.00 97.63 0.00 59.97 5.85 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_perf.4244307782
91.46 0.84 98.69 0.00 95.53 2.35 97.47 0.00 96.99 0.23 97.63 0.00 62.43 2.46 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_intr.592842568
92.19 0.73 98.69 0.00 95.53 0.00 97.47 0.00 96.99 0.00 97.63 0.00 66.83 4.40 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_full.63446717
92.79 0.60 98.69 0.00 95.53 0.00 97.47 0.00 96.99 0.00 97.63 0.00 70.44 3.61 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2167560959
93.35 0.56 98.79 0.10 95.88 0.35 99.75 2.27 97.22 0.23 97.92 0.30 70.56 0.11 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_sec_cm.3381613213
93.88 0.53 98.79 0.00 95.88 0.00 99.75 0.00 97.22 0.00 97.92 0.00 73.72 3.16 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_stress_all.439393513
94.36 0.48 98.79 0.00 95.88 0.00 99.75 0.00 97.22 0.00 97.92 0.00 76.61 2.89 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_tx_rx.1874226423
94.75 0.39 98.79 0.00 95.88 0.00 99.75 0.00 97.22 0.00 97.92 0.00 78.96 2.35 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_full.569351493
95.11 0.36 98.89 0.10 96.24 0.35 99.75 0.00 98.15 0.93 97.92 0.00 79.72 0.77 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.767633346
95.46 0.35 98.89 0.00 96.24 0.00 99.75 0.00 98.15 0.00 100.00 2.08 79.72 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.137009825
95.80 0.34 98.89 0.00 96.24 0.00 99.75 0.00 98.15 0.00 100.00 0.00 81.78 2.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.993738516
96.07 0.27 98.89 0.00 96.24 0.00 99.75 0.00 98.15 0.00 100.00 0.00 83.38 1.60 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.1535366520
96.32 0.25 98.89 0.00 96.24 0.00 99.75 0.00 98.15 0.00 100.00 0.00 84.90 1.51 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_intr.899715288
96.52 0.20 98.89 0.00 96.35 0.12 99.75 0.00 98.15 0.00 100.00 0.00 86.00 1.11 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1010028400
96.72 0.19 98.89 0.00 96.35 0.00 99.75 0.00 98.15 0.00 100.00 0.00 87.15 1.15 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_perf.244583057
96.89 0.18 98.89 0.00 96.35 0.00 99.75 0.00 98.15 0.00 100.00 0.00 88.21 1.06 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.4188696275
97.06 0.17 98.89 0.00 96.35 0.00 99.75 0.00 98.15 0.00 100.00 0.00 89.21 0.99 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3169884792
97.20 0.14 98.89 0.00 96.35 0.00 99.75 0.00 98.15 0.00 100.00 0.00 90.04 0.84 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_fifo_reset.1174999782
97.33 0.13 98.89 0.00 96.35 0.00 99.75 0.00 98.15 0.00 100.00 0.00 90.83 0.79 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.757226410
97.46 0.13 98.89 0.00 96.94 0.59 99.75 0.00 98.15 0.00 100.00 0.00 91.01 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.384080776
97.59 0.13 98.89 0.00 96.94 0.00 99.75 0.00 98.15 0.00 100.00 0.00 91.78 0.77 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_fifo_full.3284779078
97.71 0.13 99.10 0.20 97.06 0.12 99.75 0.00 98.38 0.23 100.00 0.00 91.98 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3490404789
97.82 0.11 99.10 0.00 97.06 0.00 99.75 0.00 98.38 0.00 100.00 0.00 92.66 0.68 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_full.3581659639
97.93 0.11 99.10 0.00 97.06 0.00 99.75 0.00 98.38 0.00 100.00 0.00 93.29 0.63 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.2293663972
98.03 0.10 99.10 0.00 97.41 0.35 100.00 0.25 98.38 0.00 100.00 0.00 93.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_alert_test.1795225272
98.12 0.09 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 93.86 0.56 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_stress_all.813855813
98.20 0.08 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 94.33 0.47 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2039472765
98.28 0.08 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 94.78 0.45 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2989783867
98.33 0.05 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.10 0.32 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1066082230
98.38 0.05 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.39 0.29 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_fifo_reset.2066295846
98.43 0.05 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.66 0.27 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1869466946
98.47 0.04 99.10 0.00 97.65 0.24 100.00 0.00 98.38 0.00 100.00 0.00 95.69 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.2929858984
98.51 0.04 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.94 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_full.701309123
98.54 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.14 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_intr.3425252608
98.58 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.34 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_full.245999825
98.61 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.52 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.289169230
98.64 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.70 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2835976236
98.67 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.88 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2324713760
98.69 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.04 0.16 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_stress_all.849114958
98.72 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.20 0.16 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_stress_all.2737103187
98.74 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.34 0.14 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_fifo_reset.158851921
98.76 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.45 0.11 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2609454056
98.78 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.56 0.11 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3585695470
98.80 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.67 0.11 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_stress_all.3473430077
98.81 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.76 0.09 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.4134950608
98.83 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.86 0.09 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/169.uart_fifo_reset.3105843889
98.84 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.95 0.09 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_fifo_reset.3303268047
98.86 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.04 0.09 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/58.uart_fifo_reset.16311874
98.87 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.13 0.09 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_full.1904330754
98.89 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.19 0.07 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1867224387
98.90 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.26 0.07 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/115.uart_fifo_reset.2869106788
98.91 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.33 0.07 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/124.uart_fifo_reset.702256252
98.92 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.40 0.07 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_fifo_reset.3146705481
98.93 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.46 0.07 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/73.uart_fifo_reset.3300504394
98.94 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.53 0.07 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_perf.3651870843
98.95 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.58 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1228267960
98.96 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.62 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_fifo_reset.2671856193
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.67 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/136.uart_fifo_reset.3948360726
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.71 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1836284458
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2706408111
98.99 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.80 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3200043060
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.85 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.129162502
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.89 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1185852357
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.94 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/231.uart_fifo_reset.584308000
99.02 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.98 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_intr.228827927
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.03 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1860899254
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.05 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_reset.3837091444
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.07 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2933812160
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.10 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/100.uart_fifo_reset.561073289
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.12 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/120.uart_fifo_reset.553734429
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.14 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/141.uart_fifo_reset.2670201075
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.16 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/148.uart_fifo_reset.2435229292
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.19 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_fifo_reset.701224257
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.21 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3240954570
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.23 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/160.uart_fifo_reset.1728142069
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.25 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3386000693
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.28 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_stress_all.3668336259
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.30 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/191.uart_fifo_reset.3464969388
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.32 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2773933500
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.35 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2526971218
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.37 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3418237269
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.39 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1465897069
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.41 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/240.uart_fifo_reset.262951386
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.44 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/293.uart_fifo_reset.283147320
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.46 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2279251978
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.48 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1671903073
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.50 0.02 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2453494651

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.4009040422
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2744512644
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3850795167
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1063909624
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2861419092
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.797764946
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2623164637
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.419388899
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2803790722
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3464311464
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3384030525
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.320654082
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2174291374
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.4067229770
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.2463460214
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2945299288
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2055445519
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1657825508
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2799613504
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1744595872
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2074919663
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3350359568
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1343884803
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.750355328
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3230064484
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.2294127389
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.4256012225
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1186795804
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3365798815
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.891453530
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1863884703
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3116990001
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1264505868
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3428657368
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3639934938
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2697579363
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.710111918
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4264943296
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1751080276
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1079465791
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3209871936
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2904463518
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3629772693
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1019780039
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2139288356
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.881258874
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3811529780
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1078665150
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1598982605
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.4238116049
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.714928239
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1772569859
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.198810964
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3578769217
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1445524926
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2733199896
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1812434084
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2355397482
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2721952205
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2730309777
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2498722341
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4247192827
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.950480386
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.888338578
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3207769564
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2199791563
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.585084937
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1957973836
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4186053115
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.3052995242
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3923070670
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2368013864
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3603459507
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.905731015
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1200898869
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.758709145
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2543595417
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2995474649
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.228096268
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.1231125330
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3731449180
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.1438726621
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2658592379
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.576347911
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3230701949
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2295933864
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.3650844181
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.2626263092
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1090577453
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.2411214067
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3961986953
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3983462483
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1931530045
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.988495121
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2478195374
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.3769092383
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2192494308
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.3977381321
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2526391716
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1343054170
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2455270903
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1174938959
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.4263990523
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1396177771
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.3775473076
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.590130588
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.3652015566
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2535323645
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.907907408
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.174663477
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3923794929
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2019532298
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.996808844
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2812935923
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.267737708
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.4248058603
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3280120523
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.2540512322
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3187220387
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.3501285297
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4287686912
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2738972
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.379356002
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.4082901800
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.2365958391
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3749403233
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1158030483
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1806094143
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2090378304
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.13089200
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1418527693
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2312678988
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.77650949
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3331754363
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.581295732
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3924001733
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.2260054973
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.4038010187
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3423769514
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/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_loopback.2484793234
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/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_perf.1351960343
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/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1166996856
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1841952144
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_smoke.1306436694
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_stress_all.1071213900
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.663985625
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2087105891
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_tx_rx.4006992655
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/80.uart_fifo_reset.707956045
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2951080327
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.2505628823
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/82.uart_fifo_reset.3251699824
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.265286306
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/83.uart_fifo_reset.302391036
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.751375563
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1007341764
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/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/85.uart_fifo_reset.3681265845
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.4105118577
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3689579091
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.3214472438
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/87.uart_fifo_reset.3145367546
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.1252130991
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/88.uart_fifo_reset.1332770145
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3768322617
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/89.uart_fifo_reset.4272361752
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.3007018800
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_alert_test.2015681600
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_fifo_full.1790972715
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3535347256
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_intr.3472956220
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/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_loopback.2293577142
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/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2515149143
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/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/91.uart_fifo_reset.3264248127
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.4030018386
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/92.uart_fifo_reset.4243321114
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.91675579
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.4119223650
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/94.uart_fifo_reset.674774854
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.1479008228
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2367277521
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.1921691028
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/96.uart_fifo_reset.563741354
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.1032233313
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/97.uart_fifo_reset.4103999734
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.228698706
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2803253171
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.2631063114
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/99.uart_fifo_reset.2531146324
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3336346424



Total test records in report: 1313
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_smoke.755367857 Aug 27 04:34:42 AM UTC 24 Aug 27 04:34:46 AM UTC 24 249012827 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.692908409 Aug 27 04:34:44 AM UTC 24 Aug 27 04:34:48 AM UTC 24 4802825321 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_loopback.1206177409 Aug 27 04:34:45 AM UTC 24 Aug 27 04:34:49 AM UTC 24 1285743520 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_sec_cm.3381613213 Aug 27 04:34:50 AM UTC 24 Aug 27 04:34:53 AM UTC 24 781127869 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_intr.2651120908 Aug 27 04:34:43 AM UTC 24 Aug 27 04:34:54 AM UTC 24 14907916073 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_alert_test.1795225272 Aug 27 04:34:54 AM UTC 24 Aug 27 04:34:56 AM UTC 24 12494071 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.4022858408 Aug 27 04:34:44 AM UTC 24 Aug 27 04:34:59 AM UTC 24 5269796159 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_rx_oversample.1398743318 Aug 27 04:34:43 AM UTC 24 Aug 27 04:35:01 AM UTC 24 3275662992 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.849997556 Aug 27 04:34:48 AM UTC 24 Aug 27 04:35:33 AM UTC 24 6341986771 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_smoke.1336848893 Aug 27 04:34:55 AM UTC 24 Aug 27 04:35:34 AM UTC 24 11056444605 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.4008658435 Aug 27 04:34:58 AM UTC 24 Aug 27 04:35:39 AM UTC 24 33859762556 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.954377985 Aug 27 04:35:35 AM UTC 24 Aug 27 04:35:41 AM UTC 24 791718452 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_loopback.563034279 Aug 27 04:35:37 AM UTC 24 Aug 27 04:35:42 AM UTC 24 2881825636 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.3889162265 Aug 27 04:35:31 AM UTC 24 Aug 27 04:35:45 AM UTC 24 38758138037 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_sec_cm.1550347152 Aug 27 04:35:51 AM UTC 24 Aug 27 04:35:53 AM UTC 24 65153097 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_alert_test.613353233 Aug 27 04:35:53 AM UTC 24 Aug 27 04:35:55 AM UTC 24 27120968 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3676818748 Aug 27 04:35:43 AM UTC 24 Aug 27 04:35:56 AM UTC 24 691675450 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_reset.4235698529 Aug 27 04:34:43 AM UTC 24 Aug 27 04:35:56 AM UTC 24 29019426660 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_smoke.676265038 Aug 27 04:35:53 AM UTC 24 Aug 27 04:35:58 AM UTC 24 688449054 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_tx_rx.1525046365 Aug 27 04:34:57 AM UTC 24 Aug 27 04:36:10 AM UTC 24 19051731944 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_rx_oversample.1475175102 Aug 27 04:35:02 AM UTC 24 Aug 27 04:36:11 AM UTC 24 6106169903 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_intr.2472123434 Aug 27 04:36:05 AM UTC 24 Aug 27 04:36:16 AM UTC 24 8832791946 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_intr.3127125769 Aug 27 04:35:05 AM UTC 24 Aug 27 04:36:22 AM UTC 24 41753138166 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_rx_oversample.931031640 Aug 27 04:35:59 AM UTC 24 Aug 27 04:36:22 AM UTC 24 2332171821 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.1082563276 Aug 27 04:36:22 AM UTC 24 Aug 27 04:36:26 AM UTC 24 2012445538 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_tx_rx.3648062102 Aug 27 04:35:54 AM UTC 24 Aug 27 04:36:26 AM UTC 24 35748898737 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_tx_rx.2227716902 Aug 27 04:34:42 AM UTC 24 Aug 27 04:36:31 AM UTC 24 142669991072 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_sec_cm.2583528862 Aug 27 04:36:32 AM UTC 24 Aug 27 04:36:35 AM UTC 24 238101856 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_alert_test.660204517 Aug 27 04:36:35 AM UTC 24 Aug 27 04:36:38 AM UTC 24 13140821 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_smoke.124779550 Aug 27 04:36:36 AM UTC 24 Aug 27 04:36:39 AM UTC 24 124069603 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_loopback.1475507919 Aug 27 04:36:22 AM UTC 24 Aug 27 04:36:41 AM UTC 24 7404719803 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3490404789 Aug 27 04:36:26 AM UTC 24 Aug 27 04:36:45 AM UTC 24 1485112378 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1307552355 Aug 27 04:36:17 AM UTC 24 Aug 27 04:36:48 AM UTC 24 15380020469 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_tx_rx.796006402 Aug 27 04:36:38 AM UTC 24 Aug 27 04:36:55 AM UTC 24 17500249454 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_noise_filter.3257009454 Aug 27 04:36:11 AM UTC 24 Aug 27 04:36:56 AM UTC 24 19826407166 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_noise_filter.680862710 Aug 27 04:35:29 AM UTC 24 Aug 27 04:36:58 AM UTC 24 171476784648 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_loopback.769438579 Aug 27 04:36:57 AM UTC 24 Aug 27 04:36:59 AM UTC 24 818138278 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_full.3581659639 Aug 27 04:35:55 AM UTC 24 Aug 27 04:37:00 AM UTC 24 134035585695 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.1636989744 Aug 27 04:36:57 AM UTC 24 Aug 27 04:37:00 AM UTC 24 525806721 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_noise_filter.263476679 Aug 27 04:36:49 AM UTC 24 Aug 27 04:37:06 AM UTC 24 7172158066 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_sec_cm.3021685735 Aug 27 04:37:04 AM UTC 24 Aug 27 04:37:06 AM UTC 24 82455571 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_alert_test.2348956241 Aug 27 04:37:06 AM UTC 24 Aug 27 04:37:08 AM UTC 24 11416135 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_smoke.2863704824 Aug 27 04:37:07 AM UTC 24 Aug 27 04:37:10 AM UTC 24 293988648 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.2503548712 Aug 27 04:36:50 AM UTC 24 Aug 27 04:37:11 AM UTC 24 28949138955 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_intr.4014565945 Aug 27 04:36:45 AM UTC 24 Aug 27 04:37:11 AM UTC 24 24999002741 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.1048482872 Aug 27 04:36:12 AM UTC 24 Aug 27 04:37:12 AM UTC 24 38931247980 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.4188696275 Aug 27 04:34:43 AM UTC 24 Aug 27 04:37:13 AM UTC 24 162013747430 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2324713760 Aug 27 04:36:41 AM UTC 24 Aug 27 04:37:16 AM UTC 24 20667335354 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_noise_filter.76201412 Aug 27 04:34:44 AM UTC 24 Aug 27 04:37:17 AM UTC 24 47436634444 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.869839312 Aug 27 04:37:15 AM UTC 24 Aug 27 04:37:20 AM UTC 24 5104330141 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.2479558402 Aug 27 04:37:18 AM UTC 24 Aug 27 04:37:24 AM UTC 24 970851032 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_full.245999825 Aug 27 04:36:39 AM UTC 24 Aug 27 04:37:40 AM UTC 24 44393311125 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3684713300 Aug 27 04:37:13 AM UTC 24 Aug 27 04:37:41 AM UTC 24 58175980158 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_rx_oversample.3094185688 Aug 27 04:36:42 AM UTC 24 Aug 27 04:37:41 AM UTC 24 6426624025 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_loopback.1778735573 Aug 27 04:37:21 AM UTC 24 Aug 27 04:37:41 AM UTC 24 9512422306 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_sec_cm.4009814916 Aug 27 04:37:41 AM UTC 24 Aug 27 04:37:43 AM UTC 24 296690297 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_stress_all.361152457 Aug 27 04:37:01 AM UTC 24 Aug 27 04:37:44 AM UTC 24 70743764046 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_alert_test.4123191883 Aug 27 04:37:42 AM UTC 24 Aug 27 04:37:44 AM UTC 24 144572563 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3874118462 Aug 27 04:37:34 AM UTC 24 Aug 27 04:37:45 AM UTC 24 3009229503 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_smoke.833023593 Aug 27 04:37:42 AM UTC 24 Aug 27 04:37:46 AM UTC 24 886390193 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.18070042 Aug 27 04:37:53 AM UTC 24 Aug 27 04:37:56 AM UTC 24 4528812024 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_rx_oversample.1092936755 Aug 27 04:37:14 AM UTC 24 Aug 27 04:37:57 AM UTC 24 4286840867 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_tx_rx.831308699 Aug 27 04:37:42 AM UTC 24 Aug 27 04:38:01 AM UTC 24 17209759452 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.113418889 Aug 27 04:37:58 AM UTC 24 Aug 27 04:38:02 AM UTC 24 678109101 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_noise_filter.1413646511 Aug 27 04:37:14 AM UTC 24 Aug 27 04:38:02 AM UTC 24 79621922594 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_reset.3837091444 Aug 27 04:35:00 AM UTC 24 Aug 27 04:38:02 AM UTC 24 268502185245 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_loopback.405931757 Aug 27 04:38:02 AM UTC 24 Aug 27 04:38:05 AM UTC 24 234652961 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_noise_filter.2041260711 Aug 27 04:37:53 AM UTC 24 Aug 27 04:38:07 AM UTC 24 17145943298 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2097364488 Aug 27 04:37:46 AM UTC 24 Aug 27 04:38:09 AM UTC 24 4099653459 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_alert_test.3918653964 Aug 27 04:38:08 AM UTC 24 Aug 27 04:38:10 AM UTC 24 38354064 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_full.933702741 Aug 27 04:34:57 AM UTC 24 Aug 27 04:38:11 AM UTC 24 74143022030 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_fifo_full.1058789865 Aug 27 04:37:44 AM UTC 24 Aug 27 04:38:12 AM UTC 24 82051406336 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_smoke.2711608571 Aug 27 04:38:09 AM UTC 24 Aug 27 04:38:26 AM UTC 24 5634984904 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1010028400 Aug 27 04:35:57 AM UTC 24 Aug 27 04:38:31 AM UTC 24 148096259308 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.2075681104 Aug 27 04:37:57 AM UTC 24 Aug 27 04:38:31 AM UTC 24 26600562584 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_tx_rx.3234862632 Aug 27 04:38:11 AM UTC 24 Aug 27 04:38:33 AM UTC 24 13625595763 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.767633346 Aug 27 04:37:01 AM UTC 24 Aug 27 04:38:36 AM UTC 24 4893802943 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.1601328844 Aug 27 04:38:34 AM UTC 24 Aug 27 04:38:40 AM UTC 24 6016933009 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_full.63446717 Aug 27 04:37:10 AM UTC 24 Aug 27 04:38:42 AM UTC 24 118263676314 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.2420706499 Aug 27 04:37:44 AM UTC 24 Aug 27 04:38:42 AM UTC 24 16958858721 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.2376757132 Aug 27 04:38:13 AM UTC 24 Aug 27 04:38:51 AM UTC 24 19732448405 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2006115712 Aug 27 04:38:38 AM UTC 24 Aug 27 04:38:52 AM UTC 24 6711741199 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.85808312 Aug 27 04:38:03 AM UTC 24 Aug 27 04:38:58 AM UTC 24 7525051111 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_loopback.1806368005 Aug 27 04:38:40 AM UTC 24 Aug 27 04:38:58 AM UTC 24 7128667884 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.197487051 Aug 27 04:35:57 AM UTC 24 Aug 27 04:39:00 AM UTC 24 141495114398 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_alert_test.3021292943 Aug 27 04:38:59 AM UTC 24 Aug 27 04:39:00 AM UTC 24 24598732 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_intr.2674194964 Aug 27 04:37:14 AM UTC 24 Aug 27 04:39:01 AM UTC 24 204976399858 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_smoke.1529052762 Aug 27 04:38:59 AM UTC 24 Aug 27 04:39:02 AM UTC 24 564006621 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_tx_rx.1874226423 Aug 27 04:37:08 AM UTC 24 Aug 27 04:39:12 AM UTC 24 193628191985 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.238196193 Aug 27 04:38:52 AM UTC 24 Aug 27 04:39:13 AM UTC 24 7665000182 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.3510788050 Aug 27 04:36:40 AM UTC 24 Aug 27 04:39:14 AM UTC 24 45569540360 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_intr.592842568 Aug 27 04:37:47 AM UTC 24 Aug 27 04:39:18 AM UTC 24 87066793920 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.2664069913 Aug 27 04:39:17 AM UTC 24 Aug 27 04:39:20 AM UTC 24 622212771 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1939555801 Aug 27 04:34:46 AM UTC 24 Aug 27 04:39:22 AM UTC 24 70163784835 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_intr.3191692741 Aug 27 04:38:32 AM UTC 24 Aug 27 04:39:24 AM UTC 24 13751618129 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_tx_rx.2764382296 Aug 27 04:39:01 AM UTC 24 Aug 27 04:39:24 AM UTC 24 37012043137 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.81828366 Aug 27 04:39:21 AM UTC 24 Aug 27 04:39:26 AM UTC 24 896922947 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_rx_oversample.668500961 Aug 27 04:39:12 AM UTC 24 Aug 27 04:39:27 AM UTC 24 7548687569 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_loopback.1796744279 Aug 27 04:39:23 AM UTC 24 Aug 27 04:39:29 AM UTC 24 7676027171 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.31239921 Aug 27 04:38:36 AM UTC 24 Aug 27 04:39:31 AM UTC 24 124274664804 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_alert_test.2514317829 Aug 27 04:39:30 AM UTC 24 Aug 27 04:39:32 AM UTC 24 34760204 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_smoke.1306436694 Aug 27 04:39:30 AM UTC 24 Aug 27 04:39:33 AM UTC 24 512752060 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1860899254 Aug 27 04:38:13 AM UTC 24 Aug 27 04:39:37 AM UTC 24 32258110540 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_rx_oversample.171039384 Aug 27 04:38:27 AM UTC 24 Aug 27 04:39:40 AM UTC 24 6440649514 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_perf.559600249 Aug 27 04:38:03 AM UTC 24 Aug 27 04:39:40 AM UTC 24 9154051907 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_perf.2460988028 Aug 27 04:36:23 AM UTC 24 Aug 27 04:39:53 AM UTC 24 10419614310 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.2511387299 Aug 27 04:39:19 AM UTC 24 Aug 27 04:39:54 AM UTC 24 59854311335 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2933812160 Aug 27 04:35:34 AM UTC 24 Aug 27 04:39:54 AM UTC 24 113973609150 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_perf.1128004222 Aug 27 04:34:45 AM UTC 24 Aug 27 04:39:56 AM UTC 24 18373478095 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1841952144 Aug 27 04:39:55 AM UTC 24 Aug 27 04:40:00 AM UTC 24 5111412185 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2087105891 Aug 27 04:39:57 AM UTC 24 Aug 27 04:40:03 AM UTC 24 1581886945 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_loopback.2484793234 Aug 27 04:40:01 AM UTC 24 Aug 27 04:40:05 AM UTC 24 722043230 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_full.701309123 Aug 27 04:39:01 AM UTC 24 Aug 27 04:40:06 AM UTC 24 31074746681 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.3918930089 Aug 27 04:39:34 AM UTC 24 Aug 27 04:40:07 AM UTC 24 73028526338 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_stress_all.1353726428 Aug 27 04:38:05 AM UTC 24 Aug 27 04:40:13 AM UTC 24 491569114955 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_alert_test.2966284585 Aug 27 04:40:14 AM UTC 24 Aug 27 04:40:16 AM UTC 24 13658781 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2039472765 Aug 27 04:39:02 AM UTC 24 Aug 27 04:40:18 AM UTC 24 37341637664 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_smoke.2968231318 Aug 27 04:40:17 AM UTC 24 Aug 27 04:40:20 AM UTC 24 244784894 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_full.1904330754 Aug 27 04:38:12 AM UTC 24 Aug 27 04:40:23 AM UTC 24 156078375864 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.3365722149 Aug 27 04:35:42 AM UTC 24 Aug 27 04:40:29 AM UTC 24 105436482443 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_noise_filter.1966181410 Aug 27 04:39:15 AM UTC 24 Aug 27 04:40:30 AM UTC 24 32894020591 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_noise_filter.3146438623 Aug 27 04:38:32 AM UTC 24 Aug 27 04:40:30 AM UTC 24 44114116301 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1166996856 Aug 27 04:39:55 AM UTC 24 Aug 27 04:40:33 AM UTC 24 43022125395 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.663985625 Aug 27 04:40:07 AM UTC 24 Aug 27 04:40:35 AM UTC 24 1394198997 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1404325818 Aug 27 04:39:41 AM UTC 24 Aug 27 04:40:35 AM UTC 24 4142973492 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_fifo_reset.566115958 Aug 27 04:39:38 AM UTC 24 Aug 27 04:40:35 AM UTC 24 70455179285 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2076281220 Aug 27 04:40:35 AM UTC 24 Aug 27 04:40:39 AM UTC 24 1457185832 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3169884792 Aug 27 04:34:44 AM UTC 24 Aug 27 04:40:40 AM UTC 24 134163961741 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.2671897640 Aug 27 04:40:36 AM UTC 24 Aug 27 04:40:46 AM UTC 24 1406702967 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2515149143 Aug 27 04:40:31 AM UTC 24 Aug 27 04:40:47 AM UTC 24 7194298413 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.993738516 Aug 27 04:37:25 AM UTC 24 Aug 27 04:40:48 AM UTC 24 96548897679 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_loopback.2293577142 Aug 27 04:40:40 AM UTC 24 Aug 27 04:40:49 AM UTC 24 4527159287 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_noise_filter.491012972 Aug 27 04:40:34 AM UTC 24 Aug 27 04:40:51 AM UTC 24 3995024262 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_alert_test.2015681600 Aug 27 04:40:50 AM UTC 24 Aug 27 04:40:51 AM UTC 24 49697678 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_smoke.1514104074 Aug 27 04:40:52 AM UTC 24 Aug 27 04:40:56 AM UTC 24 449367418 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_stress_all.1071213900 Aug 27 04:40:07 AM UTC 24 Aug 27 04:40:56 AM UTC 24 23515916799 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_intr.2518667939 Aug 27 04:39:41 AM UTC 24 Aug 27 04:40:57 AM UTC 24 143383928767 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_perf.4244307782 Aug 27 04:38:42 AM UTC 24 Aug 27 04:40:57 AM UTC 24 26683136811 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_full.2717659532 Aug 27 04:34:43 AM UTC 24 Aug 27 04:40:58 AM UTC 24 102735068830 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1315529318 Aug 27 04:39:27 AM UTC 24 Aug 27 04:40:58 AM UTC 24 7735422784 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_tx_rx.4057727476 Aug 27 04:40:19 AM UTC 24 Aug 27 04:41:01 AM UTC 24 79643541700 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_perf.2628668220 Aug 27 04:37:25 AM UTC 24 Aug 27 04:41:12 AM UTC 24 4618311861 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.4209049994 Aug 27 04:41:02 AM UTC 24 Aug 27 04:41:14 AM UTC 24 4448890495 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2167560959 Aug 27 04:37:12 AM UTC 24 Aug 27 04:41:16 AM UTC 24 128672399486 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.863821033 Aug 27 04:38:03 AM UTC 24 Aug 27 04:41:17 AM UTC 24 44974446802 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.1711352690 Aug 27 04:37:00 AM UTC 24 Aug 27 04:41:18 AM UTC 24 106035642965 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_intr.3472956220 Aug 27 04:40:31 AM UTC 24 Aug 27 04:41:19 AM UTC 24 44267786518 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_rx_oversample.987301863 Aug 27 04:40:58 AM UTC 24 Aug 27 04:41:19 AM UTC 24 3037995685 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.4188784482 Aug 27 04:36:23 AM UTC 24 Aug 27 04:41:21 AM UTC 24 117246604819 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.732105837 Aug 27 04:39:02 AM UTC 24 Aug 27 04:41:21 AM UTC 24 85025823449 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_alert_test.119236784 Aug 27 04:41:19 AM UTC 24 Aug 27 04:41:21 AM UTC 24 47036994 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.1934928199 Aug 27 04:40:47 AM UTC 24 Aug 27 04:41:21 AM UTC 24 8463674203 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1949350067 Aug 27 04:40:36 AM UTC 24 Aug 27 04:41:26 AM UTC 24 27370995257 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_fifo_full.2260082927 Aug 27 04:40:57 AM UTC 24 Aug 27 04:41:26 AM UTC 24 20475490327 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_smoke.1356123107 Aug 27 04:41:20 AM UTC 24 Aug 27 04:41:27 AM UTC 24 646463618 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_intr.899715288 Aug 27 04:39:13 AM UTC 24 Aug 27 04:41:29 AM UTC 24 62191829808 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.3742402955 Aug 27 04:41:10 AM UTC 24 Aug 27 04:41:32 AM UTC 24 6721650671 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.3752447910 Aug 27 04:41:30 AM UTC 24 Aug 27 04:41:34 AM UTC 24 586477358 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.2210860458 Aug 27 04:41:35 AM UTC 24 Aug 27 04:41:39 AM UTC 24 472763230 ps
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T273 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_tx_rx.854997512 Aug 27 04:41:21 AM UTC 24 Aug 27 04:41:44 AM UTC 24 32122442922 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.1115329829 Aug 27 04:41:18 AM UTC 24 Aug 27 04:41:46 AM UTC 24 7990204656 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_loopback.1914565129 Aug 27 04:41:13 AM UTC 24 Aug 27 04:41:47 AM UTC 24 8108571479 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_stress_all.221647689 Aug 27 04:40:50 AM UTC 24 Aug 27 04:41:47 AM UTC 24 99775578198 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_alert_test.1661036410 Aug 27 04:41:47 AM UTC 24 Aug 27 04:41:49 AM UTC 24 37960066 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_loopback.2156644343 Aug 27 04:41:40 AM UTC 24 Aug 27 04:41:49 AM UTC 24 3995433772 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_smoke.3179576859 Aug 27 04:41:50 AM UTC 24 Aug 27 04:41:54 AM UTC 24 633244885 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_fifo_reset.1174999782 Aug 27 04:40:30 AM UTC 24 Aug 27 04:41:59 AM UTC 24 75138808791 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2191527716 Aug 27 04:40:57 AM UTC 24 Aug 27 04:42:01 AM UTC 24 33095284747 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_reset.3187371633 Aug 27 04:41:21 AM UTC 24 Aug 27 04:42:02 AM UTC 24 122157422024 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.4134950608 Aug 27 04:41:21 AM UTC 24 Aug 27 04:42:07 AM UTC 24 21779928007 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2099236913 Aug 27 04:42:03 AM UTC 24 Aug 27 04:42:19 AM UTC 24 3479896736 ps
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T342 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_tx_rx.1089150312 Aug 27 04:41:51 AM UTC 24 Aug 27 04:42:22 AM UTC 24 65839178931 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.2690327049 Aug 27 04:42:19 AM UTC 24 Aug 27 04:42:25 AM UTC 24 1348553796 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_fifo_reset.2547969447 Aug 27 04:37:44 AM UTC 24 Aug 27 04:42:26 AM UTC 24 138666765962 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.1002398036 Aug 27 04:36:52 AM UTC 24 Aug 27 04:42:29 AM UTC 24 97867169954 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.1613002712 Aug 27 04:42:23 AM UTC 24 Aug 27 04:42:32 AM UTC 24 1444205066 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_tx_rx.1694611584 Aug 27 04:40:52 AM UTC 24 Aug 27 04:42:33 AM UTC 24 38684801077 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_perf.528262151 Aug 27 04:36:59 AM UTC 24 Aug 27 04:42:33 AM UTC 24 25058899213 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.3250605095 Aug 27 04:41:33 AM UTC 24 Aug 27 04:42:34 AM UTC 24 23748254077 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_loopback.508952772 Aug 27 04:42:26 AM UTC 24 Aug 27 04:42:34 AM UTC 24 2460956193 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_alert_test.100745345 Aug 27 04:42:34 AM UTC 24 Aug 27 04:42:36 AM UTC 24 81248929 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_tx_rx.4006992655 Aug 27 04:39:31 AM UTC 24 Aug 27 04:42:38 AM UTC 24 70835480399 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_intr.3425252608 Aug 27 04:40:58 AM UTC 24 Aug 27 04:42:39 AM UTC 24 52145417972 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_smoke.2472960212 Aug 27 04:42:34 AM UTC 24 Aug 27 04:42:42 AM UTC 24 933662155 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_fifo_reset.2671856193 Aug 27 04:42:02 AM UTC 24 Aug 27 04:42:47 AM UTC 24 21755714558 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.1473635001 Aug 27 04:40:06 AM UTC 24 Aug 27 04:42:47 AM UTC 24 246404195504 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_rx_oversample.2920655816 Aug 27 04:41:27 AM UTC 24 Aug 27 04:42:49 AM UTC 24 7148851412 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.2320902215 Aug 27 04:42:48 AM UTC 24 Aug 27 04:42:51 AM UTC 24 1845247514 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_noise_filter.3507979452 Aug 27 04:42:07 AM UTC 24 Aug 27 04:42:55 AM UTC 24 338304648009 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_rx_oversample.2411479061 Aug 27 04:42:40 AM UTC 24 Aug 27 04:42:55 AM UTC 24 2326497360 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.1989787860 Aug 27 04:42:52 AM UTC 24 Aug 27 04:42:56 AM UTC 24 715215722 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_loopback.359981592 Aug 27 04:42:55 AM UTC 24 Aug 27 04:42:57 AM UTC 24 882989294 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_stress_all.2680015922 Aug 27 04:38:53 AM UTC 24 Aug 27 04:42:59 AM UTC 24 335029927438 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_intr.2356468972 Aug 27 04:42:07 AM UTC 24 Aug 27 04:42:59 AM UTC 24 68076123850 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.2857160482 Aug 27 04:42:21 AM UTC 24 Aug 27 04:43:01 AM UTC 24 36545961002 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_alert_test.2318919766 Aug 27 04:43:00 AM UTC 24 Aug 27 04:43:01 AM UTC 24 12524171 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_stress_all.813855813 Aug 27 04:41:47 AM UTC 24 Aug 27 04:43:02 AM UTC 24 83897076716 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_full.569351493 Aug 27 04:41:21 AM UTC 24 Aug 27 04:43:03 AM UTC 24 52527497633 ps
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T279 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_stress_all.3075576135 Aug 27 04:41:19 AM UTC 24 Aug 27 04:43:08 AM UTC 24 225328896926 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_rx_oversample.795289328 Aug 27 04:43:09 AM UTC 24 Aug 27 04:43:13 AM UTC 24 1176115867 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1066082230 Aug 27 04:42:00 AM UTC 24 Aug 27 04:43:14 AM UTC 24 39945428194 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_tx_rx.3470314640 Aug 27 04:42:34 AM UTC 24 Aug 27 04:43:15 AM UTC 24 74671368702 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_intr.3560970195 Aug 27 04:43:12 AM UTC 24 Aug 27 04:43:17 AM UTC 24 4171098355 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.142858136 Aug 27 04:43:15 AM UTC 24 Aug 27 04:43:19 AM UTC 24 3594202614 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_intr.1856710171 Aug 27 04:42:43 AM UTC 24 Aug 27 04:43:23 AM UTC 24 39455273551 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_loopback.1390513678 Aug 27 04:43:20 AM UTC 24 Aug 27 04:43:24 AM UTC 24 563977090 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2010325843 Aug 27 04:42:39 AM UTC 24 Aug 27 04:43:25 AM UTC 24 58809018080 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.1714666464 Aug 27 04:43:18 AM UTC 24 Aug 27 04:43:25 AM UTC 24 944653496 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_perf.3651870843 Aug 27 04:40:40 AM UTC 24 Aug 27 04:43:27 AM UTC 24 18298377947 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_alert_test.2879926068 Aug 27 04:43:28 AM UTC 24 Aug 27 04:43:30 AM UTC 24 72996899 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.1180119542 Aug 27 04:42:50 AM UTC 24 Aug 27 04:43:31 AM UTC 24 96473745689 ps
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T367 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.897550886 Aug 27 04:42:30 AM UTC 24 Aug 27 04:43:36 AM UTC 24 8230388792 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_noise_filter.3291750900 Aug 27 04:42:48 AM UTC 24 Aug 27 04:43:40 AM UTC 24 34752986249 ps
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T287 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_noise_filter.1551473425 Aug 27 04:41:28 AM UTC 24 Aug 27 04:43:48 AM UTC 24 49177833228 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_fifo_full.1633229001 Aug 27 04:43:03 AM UTC 24 Aug 27 04:43:50 AM UTC 24 41412905655 ps
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T455 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_rx_oversample.2682830086 Aug 27 04:43:49 AM UTC 24 Aug 27 04:43:53 AM UTC 24 5281682153 ps
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T176 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2989783867 Aug 27 04:40:57 AM UTC 24 Aug 27 04:45:09 AM UTC 24 119625603311 ps
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