Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2550

1

T1

1

T2

1

T3

1

auto[UartRx]

2550

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4505	1			T1	2		T2	2		T3	2
values[1]	37	1			T34	1		T35	1		T38	1
values[2]	35	1			T34	1		T38	1		T367	1
values[3]	41	1			T9	1		T20	1		T33	1
values[4]	54	1			T9	1		T20	2		T34	2
values[5]	48	1			T9	1		T35	2		T98	1
values[6]	56	1			T35	2		T39	1		T367	3
values[7]	55	1			T9	1		T21	1		T35	2
values[8]	67	1			T21	1		T33	1		T38	1
values[9]	81	1			T21	3		T33	1		T34	1
values[10]	78	1			T9	1		T21	1		T20	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2340	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	16	1			T35	1		T83	2		T84	1
auto[UartTx]	values[2]	14	1			T34	1		T38	1		T367	1
auto[UartTx]	values[3]	14	1			T9	1		T34	1		T38	1
auto[UartTx]	values[4]	19	1			T20	2		T34	1		T35	1
auto[UartTx]	values[5]	17	1			T98	1		T360	1		T85	1
auto[UartTx]	values[6]	15	1			T35	1		T367	1		T85	1
auto[UartTx]	values[7]	22	1			T9	1		T35	1		T386	1
auto[UartTx]	values[8]	22	1			T84	1		T97	2		T85	1
auto[UartTx]	values[9]	29	1			T21	1		T34	1		T37	2
auto[UartTx]	values[10]	29	1			T21	1		T20	1		T367	1
auto[UartRx]	values[0]	2165	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	21	1			T34	1		T38	1		T84	1
auto[UartRx]	values[2]	21	1			T360	2		T379	2		T387	1
auto[UartRx]	values[3]	27	1			T20	1		T33	1		T34	2
auto[UartRx]	values[4]	35	1			T9	1		T34	1		T367	2
auto[UartRx]	values[5]	31	1			T9	1		T35	2		T84	1
auto[UartRx]	values[6]	41	1			T35	1		T39	1		T367	2
auto[UartRx]	values[7]	33	1			T21	1		T35	1		T36	1
auto[UartRx]	values[8]	45	1			T21	1		T33	1		T38	1
auto[UartRx]	values[9]	52	1			T21	2		T33	1		T37	1
auto[UartRx]	values[10]	49	1			T9	1		T35	1		T36	1