Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1835	1			T3	3		T8	6		T9	3
auto[BaudRate115200]	1473	1			T5	1		T7	2		T9	1
auto[BaudRate230400]	1539	1			T2	2		T3	3		T9	1
auto[BaudRate128Kbps]	1487	1			T11	2		T21	2		T40	1
auto[BaudRate256Kbps]	1669	1			T1	1		T11	1		T15	3
auto[BaudRate1Mbps]	1365	1			T3	3		T9	1		T11	1
auto[BaudRate1p5Mbps]	1000	1			T1	1		T3	3		T11	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1024	1			T11	10		T26	15		T28	9
freqs[25]	1023	1			T42	11		T18	6		T45	10
freqs[48]	436	1			T8	6		T44	2		T296	2
freqs[50]	436	1			T22	1		T23	2		T86	7
freqs[100]	1042	1			T7	2		T326	2		T388	11

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	171	1			T11	1		T26	2		T28	3
auto[BaudRate9600]	freqs[25]	181	1			T18	2		T45	3		T303	1
auto[BaudRate9600]	freqs[48]	69	1			T8	6		T296	1		T35	5
auto[BaudRate9600]	freqs[50]	80	1			T86	1		T19	2		T109	1
auto[BaudRate9600]	freqs[100]	151	1			T388	11		T389	17		T295	1
auto[BaudRate115200]	freqs[24]	142	1			T11	2		T26	4		T28	1
auto[BaudRate115200]	freqs[25]	158	1			T42	2		T18	1		T45	1
auto[BaudRate115200]	freqs[48]	70	1			T44	1		T35	5		T93	3
auto[BaudRate115200]	freqs[50]	45	1			T23	1		T86	1		T105	1
auto[BaudRate115200]	freqs[100]	129	1			T7	2		T309	1		T272	1
auto[BaudRate230400]	freqs[24]	148	1			T11	2		T26	1		T28	2
auto[BaudRate230400]	freqs[25]	151	1			T42	1		T18	1		T45	1
auto[BaudRate230400]	freqs[48]	58	1			T35	4		T95	1		T123	2
auto[BaudRate230400]	freqs[50]	57	1			T333	1		T105	1		T19	3
auto[BaudRate230400]	freqs[100]	150	1			T326	1		T126	2		T295	2
auto[BaudRate128Kbps]	freqs[24]	157	1			T11	2		T26	2		T28	1
auto[BaudRate128Kbps]	freqs[25]	142	1			T42	3		T18	1		T45	1
auto[BaudRate128Kbps]	freqs[48]	55	1			T35	2		T93	1		T319	1
auto[BaudRate128Kbps]	freqs[50]	56	1			T22	1		T23	1		T86	1
auto[BaudRate128Kbps]	freqs[100]	134	1			T126	1		T295	3		T359	2
auto[BaudRate256Kbps]	freqs[24]	178	1			T11	1		T26	3		T28	1
auto[BaudRate256Kbps]	freqs[25]	151	1			T42	3		T18	1		T45	1
auto[BaudRate256Kbps]	freqs[48]	74	1			T35	7		T123	1		T266	1
auto[BaudRate256Kbps]	freqs[50]	59	1			T86	2		T109	2		T110	1
auto[BaudRate256Kbps]	freqs[100]	159	1			T258	1		T373	1		T128	1
auto[BaudRate1Mbps]	freqs[24]	156	1			T11	1		T26	3		T28	1
auto[BaudRate1Mbps]	freqs[25]	175	1			T42	2		T45	2		T254	4
auto[BaudRate1Mbps]	freqs[48]	64	1			T35	1		T266	1		T180	2
auto[BaudRate1Mbps]	freqs[50]	64	1			T333	1		T109	1		T110	1
auto[BaudRate1Mbps]	freqs[100]	165	1			T272	1		T126	2		T373	1
auto[BaudRate1p5Mbps]	freqs[25]	65	1			T45	1		T254	1		T390	6
auto[BaudRate1p5Mbps]	freqs[48]	46	1			T44	1		T296	1		T35	1
auto[BaudRate1p5Mbps]	freqs[50]	75	1			T86	2		T105	3		T19	1
auto[BaudRate1p5Mbps]	freqs[100]	154	1			T326	1		T126	3		T258	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded