Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	24934497	1			T3	2		T5	11		T8	1
all_levels[1]	153634	1			T9	2		T11	2		T12	13
all_levels[2]	2080	1			T12	1		T13	5		T26	5
all_levels[3]	971	1			T13	2		T86	1		T26	2
all_levels[4]	628	1			T26	3		T42	3		T27	1
all_levels[5]	465	1			T12	3		T26	2		T27	1
all_levels[6]	342	1			T104	3		T105	1		T43	1
all_levels[7]	286	1			T12	3		T104	2		T43	1
all_levels[8]	241	1			T89	2		T106	1		T107	1
all_levels[9]	212	1			T104	5		T105	1		T106	1
all_levels[10]	156	1			T104	2		T45	1		T108	1
all_levels[11]	148	1			T86	1		T26	1		T89	1
all_levels[12]	114	1			T108	1		T109	1		T110	1
all_levels[13]	112	1			T89	1		T45	1		T111	1
all_levels[14]	110	1			T11	1		T107	1		T112	1
all_levels[15]	96	1			T45	3		T113	1		T114	1
all_levels[16]	71	1			T115	1		T116	2		T117	1
all_levels[17]	96	1			T104	1		T118	2		T108	1
all_levels[18]	85	1			T43	1		T115	1		T116	3
all_levels[19]	73	1			T111	1		T110	1		T119	1
all_levels[20]	55	1			T28	2		T120	1		T121	1
all_levels[21]	72	1			T122	2		T114	1		T123	1
all_levels[22]	71	1			T11	2		T28	1		T111	1
all_levels[23]	68	1			T107	1		T111	1		T115	1
all_levels[24]	34	1			T124	1		T120	1		T125	3
all_levels[25]	57	1			T126	2		T127	1		T128	2
all_levels[26]	37	1			T115	1		T126	1		T123	1
all_levels[27]	58	1			T43	2		T118	1		T129	1
all_levels[28]	39	1			T130	1		T96	1		T125	1
all_levels[29]	25	1			T105	1		T123	1		T128	1
all_levels[30]	21	1			T108	2		T128	1		T96	1
all_levels[31]	40	1			T123	1		T131	2		T132	1
all_levels[32]	30	1			T89	1		T123	1		T124	1
all_levels[33]	23	1			T123	1		T133	1		T121	1
all_levels[34]	24	1			T126	1		T110	1		T128	1
all_levels[35]	12	1			T45	1		T128	1		T125	1
all_levels[36]	12	1			T134	1		T98	1		T90	1
all_levels[37]	13	1			T11	1		T134	1		T135	1
all_levels[38]	24	1			T112	1		T136	1		T137	2
all_levels[39]	12	1			T138	1		T139	2		T140	1
all_levels[40]	17	1			T141	1		T142	1		T139	2
all_levels[41]	16	1			T91	1		T143	1		T144	1
all_levels[42]	19	1			T145	1		T146	1		T137	1
all_levels[43]	14	1			T96	1		T146	1		T147	1
all_levels[44]	16	1			T129	1		T148	1		T149	1
all_levels[45]	14	1			T150	1		T151	1		T152	1
all_levels[46]	16	1			T45	1		T19	3		T146	1
all_levels[47]	20	1			T129	1		T119	1		T96	1
all_levels[48]	15	1			T28	1		T153	2		T154	3
all_levels[49]	6	1			T105	1		T133	1		T143	1
all_levels[50]	6	1			T105	1		T145	1		T155	1
all_levels[51]	11	1			T130	1		T96	1		T156	1
all_levels[52]	11	1			T146	1		T149	1		T157	1
all_levels[53]	14	1			T147	1		T138	2		T158	1
all_levels[54]	6	1			T96	1		T133	2		T159	1
all_levels[55]	10	1			T133	1		T121	1		T142	1
all_levels[56]	10	1			T160	1		T161	1		T162	1
all_levels[57]	13	1			T146	1		T150	1		T163	1
all_levels[58]	7	1			T152	1		T164	1		T165	2
all_levels[59]	3	1			T166	1		T167	1		T168	1
all_levels[60]	6	1			T150	2		T169	3		T170	1
all_levels[61]	6	1			T138	1		T143	2		T171	1
all_levels[62]	3	1			T172	1		T173	1		T174	1
all_levels[63]	6	1			T112	1		T121	1		T143	1
all_levels[64]	97	1			T18	1		T111	1		T129	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25091597

1

T9

19

T11

35

T21

11

auto[1]

3909

1

T3

2

T5

11

T8

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[26]]	[auto[1]]	0	1	1
[all_levels[35] , all_levels[36] , all_levels[37]]	[auto[1]]	--	--	3
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[49] , all_levels[50]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	24931052	1			T9	17		T11	29		T21	11
all_levels[0]	auto[1]	3445	1			T3	2		T5	11		T8	1
all_levels[1]	auto[0]	153572	1			T9	2		T11	2		T12	13
all_levels[1]	auto[1]	62	1			T175	1		T176	1		T177	2
all_levels[2]	auto[0]	2052	1			T12	1		T13	5		T26	5
all_levels[2]	auto[1]	28	1			T45	1		T176	1		T178	1
all_levels[3]	auto[0]	942	1			T13	2		T86	1		T26	2
all_levels[3]	auto[1]	29	1			T45	4		T110	1		T179	2
all_levels[4]	auto[0]	598	1			T26	3		T42	3		T27	1
all_levels[4]	auto[1]	30	1			T45	2		T180	1		T169	1
all_levels[5]	auto[0]	446	1			T12	1		T26	2		T27	1
all_levels[5]	auto[1]	19	1			T12	2		T179	1		T181	2
all_levels[6]	auto[0]	329	1			T104	3		T105	1		T43	1
all_levels[6]	auto[1]	13	1			T182	1		T183	2		T184	1
all_levels[7]	auto[0]	272	1			T12	1		T104	2		T43	1
all_levels[7]	auto[1]	14	1			T12	2		T185	1		T186	2
all_levels[8]	auto[0]	219	1			T89	2		T106	1		T107	1
all_levels[8]	auto[1]	22	1			T160	3		T187	1		T188	2
all_levels[9]	auto[0]	188	1			T104	4		T105	1		T106	1
all_levels[9]	auto[1]	24	1			T104	1		T189	1		T190	1
all_levels[10]	auto[0]	145	1			T104	1		T45	1		T108	1
all_levels[10]	auto[1]	11	1			T104	1		T191	1		T192	1
all_levels[11]	auto[0]	140	1			T86	1		T26	1		T89	1
all_levels[11]	auto[1]	8	1			T182	1		T193	2		T194	1
all_levels[12]	auto[0]	112	1			T108	1		T109	1		T110	1
all_levels[12]	auto[1]	2	1			T176	1		T195	1		-	-
all_levels[13]	auto[0]	103	1			T89	1		T45	1		T111	1
all_levels[13]	auto[1]	9	1			T196	1		T197	2		T198	1
all_levels[14]	auto[0]	106	1			T11	1		T107	1		T112	1
all_levels[14]	auto[1]	4	1			T199	1		T200	2		T201	1
all_levels[15]	auto[0]	90	1			T45	1		T113	1		T114	1
all_levels[15]	auto[1]	6	1			T45	2		T202	1		T203	1
all_levels[16]	auto[0]	67	1			T115	1		T116	1		T117	1
all_levels[16]	auto[1]	4	1			T116	1		T204	1		T205	2
all_levels[17]	auto[0]	87	1			T104	1		T118	2		T108	1
all_levels[17]	auto[1]	9	1			T151	1		T206	1		T207	1
all_levels[18]	auto[0]	72	1			T43	1		T115	1		T116	1
all_levels[18]	auto[1]	13	1			T116	2		T158	1		T208	1
all_levels[19]	auto[0]	63	1			T111	1		T110	1		T119	1
all_levels[19]	auto[1]	10	1			T131	1		T209	2		T210	2
all_levels[20]	auto[0]	48	1			T28	2		T120	1		T121	1
all_levels[20]	auto[1]	7	1			T211	3		T212	1		T213	1
all_levels[21]	auto[0]	66	1			T122	1		T114	1		T123	1
all_levels[21]	auto[1]	6	1			T122	1		T214	1		T215	2
all_levels[22]	auto[0]	64	1			T11	2		T28	1		T111	1
all_levels[22]	auto[1]	7	1			T216	1		T217	1		T218	3
all_levels[23]	auto[0]	56	1			T107	1		T111	1		T115	1
all_levels[23]	auto[1]	12	1			T216	4		T219	2		T220	3
all_levels[24]	auto[0]	32	1			T124	1		T120	1		T125	2
all_levels[24]	auto[1]	2	1			T125	1		T221	1		-	-
all_levels[25]	auto[0]	49	1			T126	2		T127	1		T128	2
all_levels[25]	auto[1]	8	1			T222	1		T223	1		T224	1
all_levels[26]	auto[0]	37	1			T115	1		T126	1		T123	1
all_levels[27]	auto[0]	41	1			T43	1		T118	1		T129	1
all_levels[27]	auto[1]	17	1			T43	1		T125	11		T169	1
all_levels[28]	auto[0]	36	1			T130	1		T96	1		T125	1
all_levels[28]	auto[1]	3	1			T166	1		T154	1		T225	1
all_levels[29]	auto[0]	24	1			T105	1		T123	1		T128	1
all_levels[29]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[30]	auto[0]	18	1			T108	2		T128	1		T96	1
all_levels[30]	auto[1]	3	1			T227	2		T228	1		-	-
all_levels[31]	auto[0]	30	1			T123	1		T131	1		T132	1
all_levels[31]	auto[1]	10	1			T131	1		T216	1		T229	3
all_levels[32]	auto[0]	27	1			T89	1		T123	1		T124	1
all_levels[32]	auto[1]	3	1			T230	2		T231	1		-	-
all_levels[33]	auto[0]	20	1			T123	1		T133	1		T121	1
all_levels[33]	auto[1]	3	1			T232	2		T213	1		-	-
all_levels[34]	auto[0]	22	1			T126	1		T110	1		T128	1
all_levels[34]	auto[1]	2	1			T233	1		T234	1		-	-
all_levels[35]	auto[0]	12	1			T45	1		T128	1		T125	1
all_levels[36]	auto[0]	12	1			T134	1		T98	1		T90	1
all_levels[37]	auto[0]	13	1			T11	1		T134	1		T135	1
all_levels[38]	auto[0]	22	1			T112	1		T136	1		T137	2
all_levels[38]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[39]	auto[0]	11	1			T138	1		T139	2		T140	1
all_levels[39]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[40]	auto[0]	15	1			T141	1		T142	1		T139	2
all_levels[40]	auto[1]	2	1			T161	2		-	-		-	-
all_levels[41]	auto[0]	12	1			T91	1		T143	1		T144	1
all_levels[41]	auto[1]	4	1			T229	2		T238	2		-	-
all_levels[42]	auto[0]	18	1			T145	1		T146	1		T137	1
all_levels[42]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[43]	auto[0]	13	1			T96	1		T146	1		T147	1
all_levels[43]	auto[1]	1	1			T195	1		-	-		-	-
all_levels[44]	auto[0]	13	1			T129	1		T148	1		T149	1
all_levels[44]	auto[1]	3	1			T240	3		-	-		-	-
all_levels[45]	auto[0]	10	1			T150	1		T151	1		T152	1
all_levels[45]	auto[1]	4	1			T241	1		T242	3		-	-
all_levels[46]	auto[0]	14	1			T45	1		T19	1		T146	1
all_levels[46]	auto[1]	2	1			T19	2		-	-		-	-
all_levels[47]	auto[0]	20	1			T129	1		T119	1		T96	1
all_levels[48]	auto[0]	10	1			T28	1		T153	2		T154	1
all_levels[48]	auto[1]	5	1			T154	2		T243	3		-	-
all_levels[49]	auto[0]	6	1			T105	1		T133	1		T143	1
all_levels[50]	auto[0]	6	1			T105	1		T145	1		T155	1
all_levels[51]	auto[0]	9	1			T130	1		T96	1		T156	1
all_levels[51]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[52]	auto[0]	10	1			T146	1		T149	1		T157	1
all_levels[52]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[53]	auto[0]	12	1			T147	1		T138	2		T158	1
all_levels[53]	auto[1]	2	1			T246	1		T192	1		-	-
all_levels[54]	auto[0]	6	1			T96	1		T133	2		T159	1
all_levels[55]	auto[0]	8	1			T133	1		T121	1		T142	1
all_levels[55]	auto[1]	2	1			T247	2		-	-		-	-
all_levels[56]	auto[0]	7	1			T160	1		T161	1		T162	1
all_levels[56]	auto[1]	3	1			T248	1		T249	2		-	-
all_levels[57]	auto[0]	8	1			T146	1		T150	1		T163	1
all_levels[57]	auto[1]	5	1			T250	5		-	-		-	-
all_levels[58]	auto[0]	5	1			T152	1		T164	1		T165	1
all_levels[58]	auto[1]	2	1			T165	1		T251	1		-	-
all_levels[59]	auto[0]	3	1			T166	1		T167	1		T168	1
all_levels[60]	auto[0]	4	1			T150	2		T169	1		T170	1
all_levels[60]	auto[1]	2	1			T169	2		-	-		-	-
all_levels[61]	auto[0]	6	1			T138	1		T143	2		T171	1
all_levels[62]	auto[0]	3	1			T172	1		T173	1		T174	1
all_levels[63]	auto[0]	6	1			T112	1		T121	1		T143	1
all_levels[64]	auto[0]	78	1			T18	1		T111	1		T129	1
all_levels[64]	auto[1]	19	1			T191	1		T252	1		T253	1