Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83665	1			T1	2		T2	2		T3	1
all_pins[1]	83665	1			T1	2		T2	2		T3	1
all_pins[2]	83665	1			T1	2		T2	2		T3	1
all_pins[3]	83665	1			T1	2		T2	2		T3	1
all_pins[4]	83665	1			T1	2		T2	2		T3	1
all_pins[5]	83665	1			T1	2		T2	2		T3	1
all_pins[6]	83665	1			T1	2		T2	2		T3	1
all_pins[7]	83665	1			T1	2		T2	2		T3	1
all_pins[8]	83665	1			T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	711877	1			T1	18		T2	18		T3	8
values[0x1]	41108	1			T3	1		T5	21		T8	1
transitions[0x0=>0x1]	32440	1			T3	1		T5	20		T9	14
transitions[0x1=>0x0]	32249	1			T5	21		T8	1		T9	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	63521	1			T1	2		T2	2		T5	21
all_pins[0]	values[0x1]	20144	1			T3	1		T9	5		T11	1
all_pins[0]	transitions[0x0=>0x1]	19648	1			T3	1		T9	3		T11	1
all_pins[0]	transitions[0x1=>0x0]	980	1			T9	1		T12	1		T23	27
all_pins[1]	values[0x0]	82189	1			T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	1476	1			T9	3		T21	3		T12	4
all_pins[1]	transitions[0x0=>0x1]	1385	1			T9	1		T21	3		T12	4
all_pins[1]	transitions[0x1=>0x0]	2077	1			T9	1		T13	3		T23	1
all_pins[2]	values[0x0]	81497	1			T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	2168	1			T9	3		T13	3		T23	1
all_pins[2]	transitions[0x0=>0x1]	2124	1			T9	3		T13	3		T23	1
all_pins[2]	transitions[0x1=>0x0]	208	1			T9	1		T20	2		T19	1
all_pins[3]	values[0x0]	83413	1			T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	252	1			T9	1		T20	2		T19	1
all_pins[3]	transitions[0x0=>0x1]	208	1			T9	1		T20	1		T19	1
all_pins[3]	transitions[0x1=>0x0]	332	1			T9	1		T21	4		T20	2
all_pins[4]	values[0x0]	83289	1			T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	376	1			T9	1		T21	4		T20	3
all_pins[4]	transitions[0x0=>0x1]	304	1			T9	1		T21	4		T20	3
all_pins[4]	transitions[0x1=>0x0]	125	1			T23	1		T20	1		T17	2
all_pins[5]	values[0x0]	83468	1			T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	197	1			T23	1		T20	1		T17	4
all_pins[5]	transitions[0x0=>0x1]	167	1			T23	1		T17	4		T93	3
all_pins[5]	transitions[0x1=>0x0]	817	1			T9	2		T12	4		T26	3
all_pins[6]	values[0x0]	82818	1			T1	2		T2	2		T3	1
all_pins[6]	values[0x1]	847	1			T9	2		T12	4		T26	3
all_pins[6]	transitions[0x0=>0x1]	794	1			T9	2		T12	4		T26	3
all_pins[6]	transitions[0x1=>0x0]	255	1			T9	1		T20	2		T112	1
all_pins[7]	values[0x0]	83357	1			T1	2		T2	2		T3	1
all_pins[7]	values[0x1]	308	1			T9	1		T20	3		T112	1
all_pins[7]	transitions[0x0=>0x1]	168	1			T9	1		T20	2		T112	1
all_pins[7]	transitions[0x1=>0x0]	15200	1			T5	21		T8	1		T9	6
all_pins[8]	values[0x0]	68325	1			T1	2		T2	2		T3	1
all_pins[8]	values[0x1]	15340	1			T5	21		T8	1		T9	6
all_pins[8]	transitions[0x0=>0x1]	7642	1			T5	20		T9	2		T21	1
all_pins[8]	transitions[0x1=>0x0]	12255	1			T9	2		T21	2		T23	9