Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7177010	1			T5	9		T8	1		T9	5
all_levels[1]	2066150	1			T11	3		T21	1		T13	40
all_levels[2]	216783	1			T21	1		T86	2		T26	15
all_levels[3]	206197	1			T11	1		T86	1		T26	3
all_levels[4]	217059	1			T86	1		T26	5		T20	3
all_levels[5]	271261	1			T86	1		T26	2		T89	2
all_levels[6]	154866	1			T89	9		T42	1		T302	24
all_levels[7]	140686	1			T11	2		T86	8		T26	5
all_levels[8]	232154	1			T9	1		T11	2		T13	1
all_levels[9]	409761	1			T12	3		T13	3		T26	63
all_levels[10]	151416	1			T26	2		T20	4		T89	3
all_levels[11]	133818	1			T86	28		T26	1		T89	2
all_levels[12]	244476	1			T89	5		T42	5		T262	21
all_levels[13]	204078	1			T89	3		T42	2		T28	1
all_levels[14]	245051	1			T26	1		T89	3		T42	2
all_levels[15]	578807	1			T9	2		T26	14		T20	3
all_levels[16]	225073	1			T9	11		T13	5		T20	4
all_levels[17]	176347	1			T42	2		T27	21		T28	1
all_levels[18]	132389	1			T13	2		T89	2		T28	5
all_levels[19]	336659	1			T28	7		T262	4		T34	3
all_levels[20]	225583	1			T89	9		T42	2		T27	7
all_levels[21]	615906	1			T20	2		T104	12		T262	19
all_levels[22]	255758	1			T27	2		T28	1		T18	1
all_levels[23]	384231	1			T13	16		T20	3		T28	2
all_levels[24]	134869	1			T42	2		T28	1		T18	2
all_levels[25]	125458	1			T86	3		T27	2		T105	1
all_levels[26]	116274	1			T27	27		T28	1		T19	3
all_levels[27]	117676	1			T42	1		T105	1		T107	2
all_levels[28]	121428	1			T42	1		T28	1		T19	40
all_levels[29]	215771	1			T86	2		T105	2		T34	3
all_levels[30]	192356	1			T28	2		T104	1		T34	3
all_levels[31]	324428	1			T12	3		T28	2		T105	1
all_levels[32]	8745535	1			T11	7		T12	12		T13	42

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25091597

1

T9

19

T11

35

T21

11

auto[1]

3717

1

T5

9

T8

1

T21

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7174790	1			T9	5		T11	20		T21	9
all_levels[0]	auto[1]	2220	1			T5	9		T8	1		T21	1
all_levels[1]	auto[0]	2065917	1			T11	3		T21	1		T13	40
all_levels[1]	auto[1]	233	1			T116	2		T127	1		T308	1
all_levels[2]	auto[0]	216735	1			T21	1		T86	2		T26	15
all_levels[2]	auto[1]	48	1			T106	1		T176	2		T313	1
all_levels[3]	auto[0]	206119	1			T11	1		T86	1		T26	3
all_levels[3]	auto[1]	78	1			T373	1		T114	1		T96	15
all_levels[4]	auto[0]	217030	1			T86	1		T26	5		T20	3
all_levels[4]	auto[1]	29	1			T104	1		T381	1		T280	1
all_levels[5]	auto[0]	271224	1			T86	1		T26	2		T89	2
all_levels[5]	auto[1]	37	1			T122	2		T211	4		T393	1
all_levels[6]	auto[0]	154833	1			T89	9		T42	1		T302	24
all_levels[6]	auto[1]	33	1			T304	1		T394	2		T395	1
all_levels[7]	auto[0]	140600	1			T11	2		T86	8		T26	5
all_levels[7]	auto[1]	86	1			T95	3		T358	1		T338	1
all_levels[8]	auto[0]	232131	1			T9	1		T11	2		T13	1
all_levels[8]	auto[1]	23	1			T175	1		T301	1		T330	1
all_levels[9]	auto[0]	409728	1			T12	1		T13	3		T26	63
all_levels[9]	auto[1]	33	1			T12	2		T273	1		T132	1
all_levels[10]	auto[0]	151393	1			T26	2		T20	4		T89	3
all_levels[10]	auto[1]	23	1			T383	1		T179	1		T185	2
all_levels[11]	auto[0]	133799	1			T86	28		T26	1		T89	2
all_levels[11]	auto[1]	19	1			T180	1		T396	1		T182	1
all_levels[12]	auto[0]	244462	1			T89	5		T42	5		T262	21
all_levels[12]	auto[1]	14	1			T109	1		T285	1		T313	1
all_levels[13]	auto[0]	204046	1			T89	3		T42	2		T28	1
all_levels[13]	auto[1]	32	1			T114	1		T332	1		T305	2
all_levels[14]	auto[0]	245024	1			T26	1		T89	3		T42	2
all_levels[14]	auto[1]	27	1			T257	1		T385	4		T397	1
all_levels[15]	auto[0]	578739	1			T9	2		T26	14		T20	3
all_levels[15]	auto[1]	68	1			T320	1		T110	3		T293	1
all_levels[16]	auto[0]	225041	1			T9	11		T13	5		T20	4
all_levels[16]	auto[1]	32	1			T279	2		T131	2		T398	1
all_levels[17]	auto[0]	176329	1			T42	2		T27	20		T28	1
all_levels[17]	auto[1]	18	1			T27	1		T312	1		T399	2
all_levels[18]	auto[0]	132371	1			T13	2		T89	2		T28	5
all_levels[18]	auto[1]	18	1			T283	1		T176	1		T400	1
all_levels[19]	auto[0]	336634	1			T28	7		T262	4		T34	3
all_levels[19]	auto[1]	25	1			T108	1		T277	1		T141	1
all_levels[20]	auto[0]	225562	1			T89	9		T42	2		T27	7
all_levels[20]	auto[1]	21	1			T19	2		T401	1		T402	1
all_levels[21]	auto[0]	615888	1			T20	2		T104	10		T262	19
all_levels[21]	auto[1]	18	1			T104	2		T115	1		T294	1
all_levels[22]	auto[0]	255749	1			T27	2		T28	1		T18	1
all_levels[22]	auto[1]	9	1			T403	1		T404	1		T405	1
all_levels[23]	auto[0]	384214	1			T13	16		T20	3		T28	2
all_levels[23]	auto[1]	17	1			T406	2		T407	1		T408	2
all_levels[24]	auto[0]	134857	1			T42	2		T28	1		T18	2
all_levels[24]	auto[1]	12	1			T409	2		T164	1		T410	1
all_levels[25]	auto[0]	125442	1			T86	3		T27	2		T105	1
all_levels[25]	auto[1]	16	1			T325	1		T411	2		T412	1
all_levels[26]	auto[0]	116253	1			T27	27		T28	1		T19	2
all_levels[26]	auto[1]	21	1			T19	1		T179	1		T305	2
all_levels[27]	auto[0]	117664	1			T42	1		T105	1		T107	2
all_levels[27]	auto[1]	12	1			T413	1		T186	3		T414	1
all_levels[28]	auto[0]	121417	1			T42	1		T28	1		T19	40
all_levels[28]	auto[1]	11	1			T415	2		T188	2		T416	3
all_levels[29]	auto[0]	215757	1			T86	2		T105	2		T34	3
all_levels[29]	auto[1]	14	1			T88	1		T178	1		T154	1
all_levels[30]	auto[0]	192349	1			T28	2		T104	1		T34	3
all_levels[30]	auto[1]	7	1			T176	1		T409	1		T174	3
all_levels[31]	auto[0]	324407	1			T12	2		T28	2		T105	1
all_levels[31]	auto[1]	21	1			T12	1		T270	1		T179	1
all_levels[32]	auto[0]	8745093	1			T11	7		T12	11		T13	41
all_levels[32]	auto[1]	442	1			T12	1		T13	1		T86	1