Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	665	1			T9	7		T20	7		T35	7
all_values[1]	665	1			T9	7		T20	7		T35	7
all_values[2]	665	1			T9	7		T20	7		T35	7
all_values[3]	665	1			T9	7		T20	7		T35	7
all_values[4]	665	1			T9	7		T20	7		T35	7
all_values[5]	665	1			T9	7		T20	7		T35	7
all_values[6]	665	1			T9	7		T20	7		T35	7
all_values[7]	665	1			T9	7		T20	7		T35	7
all_values[8]	665	1			T9	7		T20	7		T35	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3312

1

T9

31

T20

32

T35

17

auto[1]

2673

1

T9

32

T20

31

T35

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1931

1

T9

21

T20

18

T35

25

auto[1]

4054

1

T9

42

T20

45

T35

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3500

1

T9

36

T20

32

T35

41

auto[1]

2485

1

T9

27

T20

31

T35

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	203	1			T9	1		T20	3		T35	2
all_values[0]	auto[0]	auto[1]	auto[1]	169	1			T9	2		T20	2		T35	1
all_values[0]	auto[1]	auto[0]	auto[1]	157	1			T9	1		T20	2		T35	1
all_values[0]	auto[1]	auto[1]	auto[1]	136	1			T9	3		T35	3		T38	1
all_values[1]	auto[0]	auto[0]	auto[0]	207	1			T9	2		T20	3		T35	1
all_values[1]	auto[0]	auto[1]	auto[0]	171	1			T20	2		T35	2		T38	2
all_values[1]	auto[1]	auto[0]	auto[1]	158	1			T9	3		T20	1		T35	4
all_values[1]	auto[1]	auto[1]	auto[1]	129	1			T9	2		T20	1		T38	1
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T39	2		T96	2		T97	1
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T9	1		T20	1		T37	1
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T9	1		T20	1		T35	2
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T9	2		T35	2		T38	2
all_values[2]	auto[1]	auto[0]	auto[1]	158	1			T9	2		T20	3		T35	2
all_values[2]	auto[1]	auto[1]	auto[1]	118	1			T9	1		T20	2		T35	1
all_values[3]	auto[0]	auto[0]	auto[0]	126	1			T9	1		T37	1		T39	2
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T20	2		T39	1		T84	1
all_values[3]	auto[0]	auto[1]	auto[0]	113	1			T9	5		T35	7		T37	1
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T37	1		T98	2		T84	1
all_values[3]	auto[1]	auto[0]	auto[1]	174	1			T20	3		T38	2		T39	1
all_values[3]	auto[1]	auto[1]	auto[1]	105	1			T9	1		T20	2		T37	1
all_values[4]	auto[0]	auto[0]	auto[0]	146	1			T9	2		T20	1		T37	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1			T39	1		T98	2		T97	2
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T9	1		T20	1		T35	3
all_values[4]	auto[0]	auto[1]	auto[1]	62	1			T9	1		T20	1		T35	1
all_values[4]	auto[1]	auto[0]	auto[1]	151	1			T9	2		T20	2		T35	1
all_values[4]	auto[1]	auto[1]	auto[1]	111	1			T9	1		T20	2		T35	2
all_values[5]	auto[0]	auto[0]	auto[0]	172	1			T9	4		T20	1		T35	1
all_values[5]	auto[0]	auto[0]	auto[1]	41	1			T37	1		T97	1		T99	1
all_values[5]	auto[0]	auto[1]	auto[0]	121	1			T9	3		T20	4		T35	6
all_values[5]	auto[0]	auto[1]	auto[1]	72	1			T38	2		T96	2		T98	1
all_values[5]	auto[1]	auto[0]	auto[1]	155	1			T37	1		T39	2		T98	3
all_values[5]	auto[1]	auto[1]	auto[1]	104	1			T20	2		T38	1		T96	1
all_values[6]	auto[0]	auto[0]	auto[0]	136	1			T20	3		T37	3		T38	1
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T9	2		T84	1		T100	2
all_values[6]	auto[0]	auto[1]	auto[0]	90	1			T20	1		T35	3		T38	1
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T9	1		T20	1		T35	1
all_values[6]	auto[1]	auto[0]	auto[1]	166	1			T9	4		T20	1		T37	1
all_values[6]	auto[1]	auto[1]	auto[1]	115	1			T20	1		T35	3		T38	1
all_values[7]	auto[0]	auto[0]	auto[0]	147	1			T37	1		T38	2		T96	1
all_values[7]	auto[0]	auto[0]	auto[1]	63	1			T9	1		T35	1		T37	1
all_values[7]	auto[0]	auto[1]	auto[0]	104	1			T9	2		T20	1		T98	2
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T20	1		T35	2		T39	2
all_values[7]	auto[1]	auto[0]	auto[1]	147	1			T9	3		T20	2		T35	4
all_values[7]	auto[1]	auto[1]	auto[1]	125	1			T9	1		T20	3		T39	1
all_values[8]	auto[0]	auto[0]	auto[1]	220	1			T9	1		T20	3		T38	3
all_values[8]	auto[0]	auto[1]	auto[1]	169	1			T9	3		T35	6		T37	2
all_values[8]	auto[1]	auto[0]	auto[1]	163	1			T9	1		T20	1		T37	1
all_values[8]	auto[1]	auto[1]	auto[1]	113	1			T9	2		T20	3		T35	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal