Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66403745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15713862

1

T1

8

T2

3

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80888578	1			T1	554		T2	1		T3	1
values[0x0]	596691	1			T1	6		T2	6		T4	22
values[0x1]	632338	1			T1	7		T2	7		T4	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46010932	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36106675

1

T1

182

T2

5

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	297123	1			T6	25		T9	9		T11	3
valid_sources[0x01]	356825	1			T6	17		T9	8		T11	5
valid_sources[0x02]	305434	1			T6	26		T9	5		T14	11
valid_sources[0x03]	301513	1			T6	12		T9	7		T11	3
valid_sources[0x04]	377248	1			T6	25		T11	5		T14	20
valid_sources[0x05]	297054	1			T6	25		T9	11		T11	2
valid_sources[0x06]	317631	1			T6	26		T9	1		T11	1
valid_sources[0x07]	328509	1			T6	22		T9	5		T11	2
valid_sources[0x08]	315875	1			T6	27		T9	7		T11	7
valid_sources[0x09]	281785	1			T4	19		T6	28		T9	5
valid_sources[0x0a]	342785	1			T6	15		T9	2		T11	6
valid_sources[0x0b]	309072	1			T4	2		T6	18		T8	1
valid_sources[0x0c]	274805	1			T6	14		T9	5		T11	6
valid_sources[0x0d]	303335	1			T6	25		T9	1		T11	1
valid_sources[0x0e]	367189	1			T6	15		T9	4		T11	2
valid_sources[0x0f]	305794	1			T6	33		T9	2		T11	4
valid_sources[0x10]	340100	1			T6	19		T9	3		T11	1
valid_sources[0x11]	288642	1			T4	9		T6	20		T9	5
valid_sources[0x12]	328537	1			T6	24		T9	4		T10	1
valid_sources[0x13]	316816	1			T6	29		T9	2		T11	3
valid_sources[0x14]	354307	1			T6	20		T9	15		T14	12
valid_sources[0x15]	367438	1			T6	17		T9	8		T11	4
valid_sources[0x16]	385684	1			T6	16		T9	5		T11	1
valid_sources[0x17]	328531	1			T6	17		T11	5		T14	12
valid_sources[0x18]	305640	1			T4	2		T6	20		T9	3
valid_sources[0x19]	296018	1			T6	22		T11	6		T14	12
valid_sources[0x1a]	314448	1			T6	16		T9	8		T11	2
valid_sources[0x1b]	335737	1			T6	18		T11	2		T14	18
valid_sources[0x1c]	285588	1			T6	21		T9	14		T11	2
valid_sources[0x1d]	277413	1			T4	6		T6	25		T9	2
valid_sources[0x1e]	303851	1			T6	28		T9	4		T10	1
valid_sources[0x1f]	327033	1			T6	26		T9	2		T11	2
valid_sources[0x20]	320455	1			T6	19		T9	7		T11	2
valid_sources[0x21]	311147	1			T6	26		T9	3		T11	4
valid_sources[0x22]	323601	1			T6	45		T9	9		T11	1
valid_sources[0x23]	385556	1			T6	36		T7	6748		T9	1
valid_sources[0x24]	459045	1			T6	17		T9	2		T11	4
valid_sources[0x25]	370132	1			T6	22		T11	6		T14	15
valid_sources[0x26]	331322	1			T6	16		T9	9		T11	2
valid_sources[0x27]	285885	1			T6	20		T9	1		T11	6
valid_sources[0x28]	303671	1			T4	3		T6	15		T9	9
valid_sources[0x29]	317266	1			T6	23		T9	3		T11	2
valid_sources[0x2a]	441959	1			T6	25		T11	5		T14	13
valid_sources[0x2b]	323156	1			T6	9		T11	4		T14	8
valid_sources[0x2c]	282030	1			T6	27		T11	9		T14	8
valid_sources[0x2d]	281910	1			T6	19		T9	2		T11	6
valid_sources[0x2e]	311714	1			T6	25		T9	1		T11	2
valid_sources[0x2f]	299571	1			T6	32		T9	2		T11	4
valid_sources[0x30]	397081	1			T6	18		T9	7		T11	5
valid_sources[0x31]	302410	1			T3	1		T6	14		T9	1
valid_sources[0x32]	469861	1			T2	2		T6	33		T8	1
valid_sources[0x33]	293850	1			T6	18		T9	5		T11	7
valid_sources[0x34]	307001	1			T6	14		T9	5		T11	8
valid_sources[0x35]	271167	1			T4	3		T6	17		T9	1
valid_sources[0x36]	339478	1			T5	2		T6	13		T9	1
valid_sources[0x37]	297824	1			T6	19		T9	12		T11	3
valid_sources[0x38]	323209	1			T6	12		T7	1057		T9	6
valid_sources[0x39]	300226	1			T6	11		T9	1		T11	12
valid_sources[0x3a]	326989	1			T6	23		T9	13		T11	6
valid_sources[0x3b]	301624	1			T6	21		T9	3		T11	1
valid_sources[0x3c]	293001	1			T6	21		T9	2		T11	1
valid_sources[0x3d]	321541	1			T6	13		T9	7		T11	2
valid_sources[0x3e]	294022	1			T6	19		T9	1		T11	6
valid_sources[0x3f]	318985	1			T6	21		T9	5		T11	1
valid_sources[0x40]	277325	1			T6	20		T11	4		T14	17
valid_sources[0x41]	297795	1			T6	26		T9	5		T11	2
valid_sources[0x42]	396367	1			T6	21		T9	4		T11	1
valid_sources[0x43]	290647	1			T6	22		T9	5		T10	1
valid_sources[0x44]	304899	1			T6	25		T9	10		T11	3
valid_sources[0x45]	434163	1			T6	16		T9	3		T11	7
valid_sources[0x46]	440609	1			T6	23		T11	3		T14	14
valid_sources[0x47]	286755	1			T6	13		T9	2		T11	6
valid_sources[0x48]	357019	1			T6	27		T9	1		T11	4
valid_sources[0x49]	320392	1			T6	16		T11	6		T14	10
valid_sources[0x4a]	289649	1			T6	27		T9	3		T31	1
valid_sources[0x4b]	337206	1			T6	36		T9	5		T11	4
valid_sources[0x4c]	304852	1			T6	16		T9	1		T10	1
valid_sources[0x4d]	334713	1			T6	23		T9	2		T11	1
valid_sources[0x4e]	436561	1			T6	28		T9	5		T11	9
valid_sources[0x4f]	305041	1			T6	21		T9	4		T11	4
valid_sources[0x50]	362167	1			T6	23		T9	6		T11	7
valid_sources[0x51]	302359	1			T6	24		T9	1		T11	4
valid_sources[0x52]	304031	1			T6	13		T8	1		T9	14
valid_sources[0x53]	302621	1			T6	23		T11	10		T14	13
valid_sources[0x54]	295303	1			T5	264		T6	21		T9	5
valid_sources[0x55]	275628	1			T6	14		T9	11		T11	6
valid_sources[0x56]	300701	1			T6	26		T9	4		T13	2
valid_sources[0x57]	281285	1			T6	33		T9	5		T11	5
valid_sources[0x58]	314110	1			T6	26		T9	7		T11	6
valid_sources[0x59]	290430	1			T4	1		T6	25		T9	2
valid_sources[0x5a]	310974	1			T6	13		T9	4		T11	5
valid_sources[0x5b]	287268	1			T4	5		T6	30		T9	1
valid_sources[0x5c]	350685	1			T6	24		T9	4		T11	4
valid_sources[0x5d]	343112	1			T6	20		T9	3		T11	3
valid_sources[0x5e]	274597	1			T6	23		T8	1		T9	3
valid_sources[0x5f]	289243	1			T2	1		T6	20		T9	4
valid_sources[0x60]	307807	1			T6	12		T11	5		T14	7
valid_sources[0x61]	286708	1			T2	1		T4	2		T6	19
valid_sources[0x62]	277512	1			T6	27		T9	10		T11	4
valid_sources[0x63]	340478	1			T6	24		T9	2		T11	5
valid_sources[0x64]	295286	1			T6	38		T9	4		T11	2
valid_sources[0x65]	334431	1			T6	16		T9	4		T11	5
valid_sources[0x66]	302459	1			T6	34		T9	1		T11	4
valid_sources[0x67]	312491	1			T6	14		T8	2		T9	9
valid_sources[0x68]	272293	1			T6	27		T9	1		T11	1
valid_sources[0x69]	303927	1			T6	17		T9	6		T11	6
valid_sources[0x6a]	309533	1			T6	26		T9	3		T11	4
valid_sources[0x6b]	293994	1			T6	26		T9	13		T11	2
valid_sources[0x6c]	288857	1			T6	30		T11	8		T14	17
valid_sources[0x6d]	301705	1			T4	19		T6	16		T9	4
valid_sources[0x6e]	282326	1			T6	18		T9	2		T11	5
valid_sources[0x6f]	287421	1			T4	5		T6	10		T11	3
valid_sources[0x70]	288335	1			T6	22		T9	3		T14	10
valid_sources[0x71]	280801	1			T6	15		T9	5		T11	4
valid_sources[0x72]	283655	1			T6	19		T8	1		T9	2
valid_sources[0x73]	296254	1			T6	38		T9	5		T11	3
valid_sources[0x74]	381120	1			T6	17		T9	2		T11	6
valid_sources[0x75]	297848	1			T6	17		T9	3		T11	5
valid_sources[0x76]	325141	1			T4	1		T6	28		T9	9
valid_sources[0x77]	282747	1			T6	20		T11	5		T14	10
valid_sources[0x78]	275283	1			T6	32		T9	6		T11	9
valid_sources[0x79]	283701	1			T6	12		T14	12		T23	9
valid_sources[0x7a]	340358	1			T6	18		T11	5		T14	15
valid_sources[0x7b]	282389	1			T6	22		T9	7		T11	5
valid_sources[0x7c]	290121	1			T6	26		T9	1		T10	1
valid_sources[0x7d]	317462	1			T6	30		T9	5		T14	7
valid_sources[0x7e]	356146	1			T2	1		T6	16		T9	11
valid_sources[0x7f]	295664	1			T6	26		T11	6		T14	9
valid_sources[0x80]	320131	1			T4	3		T6	24		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14942595

1

T1

4

T2

1

T3

1

values[0x0]

all_enables

biggest_size

410961

1

T1

2

T2

2

T4

17

values[0x1]

all_enables

biggest_size

360306

1

T1

2

T4

8

T5

46