Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	951507	0	0
ctrl_rd_A	2147483647	24990	0	0
intr_enable_rd_A	2147483647	23830	0	0
ovrd_rd_A	2147483647	22724	0	0
timeout_ctrl_rd_A	2147483647	23067	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	951507	0	0
T16	902125	0	0	0
T19	77982	2699	0	0
T20	0	5606	0	0
T21	621748	0	0	0
T27	297134	0	0	0
T29	0	1462	0	0
T30	766888	0	0	0
T33	0	16732	0	0
T34	0	2378	0	0
T35	0	7524	0	0
T36	0	16316	0	0
T37	0	4598	0	0
T38	0	21032	0	0
T39	0	8809	0	0
T40	352172	0	0	0
T41	51853	0	0	0
T42	650471	0	0	0
T43	46493	0	0	0
T44	356479	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24990	0	0
T20	238735	722	0	0
T26	444232	0	0	0
T34	0	367	0	0
T35	0	858	0	0
T50	717858	0	0	0
T87	4011	0	0	0
T88	0	864	0	0
T89	0	475	0	0
T90	0	1649	0	0
T91	0	229	0	0
T92	0	540	0	0
T93	0	312	0	0
T94	0	1564	0	0
T95	207375	0	0	0
T96	116834	0	0	0
T97	430800	0	0	0
T98	237809	0	0	0
T99	181911	0	0	0
T100	260719	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23830	0	0
T20	238735	746	0	0
T26	444232	0	0	0
T34	0	405	0	0
T35	0	752	0	0
T50	717858	0	0	0
T87	4011	0	0	0
T88	0	766	0	0
T89	0	452	0	0
T90	0	1239	0	0
T91	0	215	0	0
T92	0	564	0	0
T95	207375	0	0	0
T96	116834	0	0	0
T97	430800	0	0	0
T98	237809	0	0	0
T99	181911	0	0	0
T100	260719	0	0	0
T101	0	8	0	0
T102	0	14	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22724	0	0
T20	238735	796	0	0
T26	444232	0	0	0
T34	0	398	0	0
T35	0	816	0	0
T50	717858	0	0	0
T87	4011	0	0	0
T88	0	979	0	0
T89	0	457	0	0
T90	0	1445	0	0
T91	0	242	0	0
T92	0	557	0	0
T93	0	297	0	0
T94	0	1277	0	0
T95	207375	0	0	0
T96	116834	0	0	0
T97	430800	0	0	0
T98	237809	0	0	0
T99	181911	0	0	0
T100	260719	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23067	0	0
T20	238735	676	0	0
T26	444232	0	0	0
T34	0	367	0	0
T35	0	826	0	0
T50	717858	0	0	0
T87	4011	0	0	0
T88	0	875	0	0
T89	0	444	0	0
T90	0	1635	0	0
T91	0	260	0	0
T92	0	493	0	0
T93	0	379	0	0
T94	0	1404	0	0
T95	207375	0	0	0
T96	116834	0	0	0
T97	430800	0	0	0
T98	237809	0	0	0
T99	181911	0	0	0
T100	260719	0	0	0