Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81168	1			T3	2		T4	2		T5	2
all_values[1]	81168	1			T3	2		T4	2		T5	2
all_values[2]	81168	1			T3	2		T4	2		T5	2
all_values[3]	81168	1			T3	2		T4	2		T5	2
all_values[4]	81168	1			T3	2		T4	2		T5	2
all_values[5]	81168	1			T3	2		T4	2		T5	2
all_values[6]	81168	1			T3	2		T4	2		T5	2
all_values[7]	81168	1			T3	2		T4	2		T5	2
all_values[8]	81168	1			T3	2		T4	2		T5	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

360172

1

T3

18

T4

18

T5

18

auto[1]

370340

1

T10

5

T11

86

T15

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

655027

1

T3

13

T4

13

T5

13

auto[1]

75485

1

T3

5

T4

5

T5

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	21644	1			T12	3		T30	4		T75	6
all_values[0]	auto[0]	auto[1]	18833	1			T3	2		T4	2		T5	2
all_values[0]	auto[1]	auto[0]	21309	1			T107	1		T31	8		T114	2
all_values[0]	auto[1]	auto[1]	19382	1			T11	11		T17	1		T12	7
all_values[1]	auto[0]	auto[0]	39894	1			T3	2		T4	2		T5	2
all_values[1]	auto[0]	auto[1]	1348	1			T11	3		T13	3		T21	2
all_values[1]	auto[1]	auto[0]	38572	1			T11	5		T15	1		T12	7
all_values[1]	auto[1]	auto[1]	1354	1			T11	3		T13	1		T75	13
all_values[2]	auto[0]	auto[0]	35628	1			T3	1		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	2240	1			T3	1		T4	1		T5	1
all_values[2]	auto[1]	auto[0]	41181	1			T10	1		T11	9		T15	1
all_values[2]	auto[1]	auto[1]	2119	1			T11	1		T12	1		T13	2
all_values[3]	auto[0]	auto[0]	37587	1			T3	2		T4	2		T5	2
all_values[3]	auto[0]	auto[1]	264	1			T11	4		T21	3		T19	1
all_values[3]	auto[1]	auto[0]	43057	1			T10	1		T11	9		T17	1
all_values[3]	auto[1]	auto[1]	260	1			T11	2		T21	2		T18	1
all_values[4]	auto[0]	auto[0]	39818	1			T3	2		T4	2		T5	2
all_values[4]	auto[0]	auto[1]	414	1			T11	3		T13	3		T21	2
all_values[4]	auto[1]	auto[0]	40601	1			T11	4		T17	1		T12	8
all_values[4]	auto[1]	auto[1]	335	1			T11	2		T13	1		T21	2
all_values[5]	auto[0]	auto[0]	39781	1			T3	2		T4	2		T5	2
all_values[5]	auto[0]	auto[1]	187	1			T11	3		T13	2		T21	2
all_values[5]	auto[1]	auto[0]	41053	1			T10	1		T11	10		T15	1
all_values[5]	auto[1]	auto[1]	147	1			T13	1		T21	2		T40	1
all_values[6]	auto[0]	auto[0]	36226	1			T3	2		T4	2		T5	2
all_values[6]	auto[0]	auto[1]	198	1			T11	3		T13	1		T21	3
all_values[6]	auto[1]	auto[0]	44601	1			T11	5		T12	5		T43	1
all_values[6]	auto[1]	auto[1]	143	1			T11	2		T13	2		T21	2
all_values[7]	auto[0]	auto[0]	42397	1			T3	2		T4	2		T5	2
all_values[7]	auto[0]	auto[1]	343	1			T11	1		T29	3		T21	1
all_values[7]	auto[1]	auto[0]	38108	1			T10	1		T11	9		T24	13
all_values[7]	auto[1]	auto[1]	320	1			T11	2		T13	2		T29	2
all_values[8]	auto[0]	auto[0]	28063	1			T30	1		T46	8		T33	12
all_values[8]	auto[0]	auto[1]	15307	1			T3	2		T4	2		T5	2
all_values[8]	auto[1]	auto[0]	25507	1			T12	3		T13	1		T30	5
all_values[8]	auto[1]	auto[1]	12291	1			T10	1		T11	12		T15	1