Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2595

1

T1

1

T2

11

T3

1

auto[UartRx]

2595

1

T1

1

T2

11

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4506	1			T1	2		T2	22		T3	2
values[1]	51	1			T39	2		T41	1		T406	1
values[2]	47	1			T31	1		T21	1		T37	3
values[3]	57	1			T11	1		T31	1		T21	1
values[4]	56	1			T31	1		T37	1		T40	1
values[5]	51	1			T31	1		T37	1		T38	2
values[6]	69	1			T11	1		T13	1		T36	1
values[7]	72	1			T13	2		T21	1		T37	1
values[8]	67	1			T11	2		T13	1		T38	1
values[9]	75	1			T13	1		T36	1		T37	2
values[10]	95	1			T13	1		T37	1		T38	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2347	1			T1	1		T2	11		T3	1
auto[UartTx]	values[1]	23	1			T39	1		T41	1		T416	1
auto[UartTx]	values[2]	13	1			T21	1		T37	1		T100	1
auto[UartTx]	values[3]	13	1			T406	1		T87	1		T417	1
auto[UartTx]	values[4]	26	1			T37	1		T87	1		T100	2
auto[UartTx]	values[5]	15	1			T38	1		T41	1		T418	1
auto[UartTx]	values[6]	23	1			T341	1		T99	1		T86	1
auto[UartTx]	values[7]	25	1			T39	1		T41	2		T90	1
auto[UartTx]	values[8]	33	1			T13	1		T41	1		T86	2
auto[UartTx]	values[9]	29	1			T36	1		T99	1		T86	1
auto[UartTx]	values[10]	33	1			T13	1		T37	1		T38	1
auto[UartRx]	values[0]	2159	1			T1	1		T2	11		T3	1
auto[UartRx]	values[1]	28	1			T39	1		T406	1		T100	1
auto[UartRx]	values[2]	34	1			T31	1		T37	2		T38	1
auto[UartRx]	values[3]	44	1			T11	1		T31	1		T21	1
auto[UartRx]	values[4]	30	1			T31	1		T40	1		T99	1
auto[UartRx]	values[5]	36	1			T31	1		T37	1		T38	1
auto[UartRx]	values[6]	46	1			T11	1		T13	1		T36	1
auto[UartRx]	values[7]	47	1			T13	2		T21	1		T37	1
auto[UartRx]	values[8]	34	1			T11	2		T38	1		T39	1
auto[UartRx]	values[9]	46	1			T13	1		T37	2		T39	1
auto[UartRx]	values[10]	62	1			T341	1		T99	3		T406	1