Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2070	1			T15	7		T17	6		T12	1
auto[BaudRate115200]	1508	1			T5	1		T10	12		T14	1
auto[BaudRate230400]	1504	1			T8	1		T10	3		T14	1
auto[BaudRate128Kbps]	1555	1			T9	1		T17	3		T12	1
auto[BaudRate256Kbps]	1673	1			T3	1		T8	1		T10	9
auto[BaudRate1Mbps]	1428	1			T3	1		T4	2		T9	1
auto[BaudRate1p5Mbps]	1110	1			T5	1		T10	9		T11	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1035	1			T10	36		T14	2		T11	9
freqs[25]	894	1			T44	2		T75	6		T114	6
freqs[48]	621	1			T5	2		T28	3		T371	2
freqs[50]	408	1			T42	2		T374	2		T276	19
freqs[100]	1126	1			T9	2		T359	2		T333	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	189	1			T13	1		T32	3		T33	1
auto[BaudRate9600]	freqs[25]	209	1			T75	1		T114	3		T145	4
auto[BaudRate9600]	freqs[48]	139	1			T28	3		T47	16		T295	1
auto[BaudRate9600]	freqs[50]	87	1			T374	2		T113	1		T121	1
auto[BaudRate9600]	freqs[100]	210	1			T31	1		T105	1		T419	9
auto[BaudRate115200]	freqs[24]	166	1			T10	12		T14	1		T11	6
auto[BaudRate115200]	freqs[25]	129	1			T75	1		T22	1		T40	1
auto[BaudRate115200]	freqs[48]	67	1			T5	1		T371	1		T29	1
auto[BaudRate115200]	freqs[50]	50	1			T42	1		T276	5		T343	1
auto[BaudRate115200]	freqs[100]	151	1			T31	1		T105	1		T419	3
auto[BaudRate230400]	freqs[24]	150	1			T10	3		T14	1		T16	1
auto[BaudRate230400]	freqs[25]	119	1			T114	1		T22	1		T388	1
auto[BaudRate230400]	freqs[48]	78	1			T29	1		T295	1		T420	3
auto[BaudRate230400]	freqs[50]	49	1			T276	2		T137	1		T121	1
auto[BaudRate230400]	freqs[100]	153	1			T359	1		T333	1		T31	2
auto[BaudRate128Kbps]	freqs[24]	142	1			T13	1		T33	4		T20	1
auto[BaudRate128Kbps]	freqs[25]	119	1			T75	1		T114	1		T145	2
auto[BaudRate128Kbps]	freqs[48]	75	1			T371	1		T29	1		T420	3
auto[BaudRate128Kbps]	freqs[50]	44	1			T42	1		T276	1		T351	1
auto[BaudRate128Kbps]	freqs[100]	151	1			T9	1		T105	3		T314	3
auto[BaudRate256Kbps]	freqs[24]	166	1			T10	9		T11	1		T13	1
auto[BaudRate256Kbps]	freqs[25]	134	1			T44	2		T75	2		T145	2
auto[BaudRate256Kbps]	freqs[48]	85	1			T29	1		T280	1		T420	9
auto[BaudRate256Kbps]	freqs[50]	44	1			T276	1		T137	1		T113	3
auto[BaudRate256Kbps]	freqs[100]	145	1			T359	1		T333	1		T31	2
auto[BaudRate1Mbps]	freqs[24]	140	1			T10	3		T11	1		T13	1
auto[BaudRate1Mbps]	freqs[25]	131	1			T75	1		T145	1		T40	1
auto[BaudRate1Mbps]	freqs[48]	85	1			T29	3		T283	1		T310	1
auto[BaudRate1Mbps]	freqs[50]	69	1			T276	6		T137	2		T351	1
auto[BaudRate1Mbps]	freqs[100]	162	1			T9	1		T316	2		T314	1
auto[BaudRate1p5Mbps]	freqs[25]	53	1			T114	1		T40	2		T273	1
auto[BaudRate1p5Mbps]	freqs[48]	92	1			T5	1		T29	2		T420	6
auto[BaudRate1p5Mbps]	freqs[50]	65	1			T276	4		T137	2		T113	1
auto[BaudRate1p5Mbps]	freqs[100]	154	1			T105	1		T314	3		T419	6

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded