Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	22207595	1			T10	8		T11	10		T15	1
all_levels[1]	140638	1			T75	2		T32	17		T46	9
all_levels[2]	2173	1			T11	1		T32	7		T46	4
all_levels[3]	940	1			T75	1		T46	1		T33	5
all_levels[4]	596	1			T12	1		T32	4		T46	2
all_levels[5]	448	1			T32	2		T46	1		T33	1
all_levels[6]	339	1			T32	1		T46	2		T33	2
all_levels[7]	318	1			T30	1		T32	1		T33	1
all_levels[8]	229	1			T32	1		T46	1		T33	1
all_levels[9]	197	1			T30	2		T33	1		T104	1
all_levels[10]	170	1			T104	1		T29	1		T105	1
all_levels[11]	149	1			T75	1		T106	2		T23	2
all_levels[12]	142	1			T107	1		T91	1		T106	1
all_levels[13]	101	1			T33	1		T108	1		T23	1
all_levels[14]	87	1			T23	3		T109	1		T110	1
all_levels[15]	115	1			T33	1		T91	1		T36	1
all_levels[16]	76	1			T29	1		T106	1		T111	1
all_levels[17]	79	1			T105	1		T112	1		T113	1
all_levels[18]	74	1			T114	1		T29	1		T94	1
all_levels[19]	58	1			T26	2		T33	1		T94	1
all_levels[20]	55	1			T20	1		T94	1		T110	2
all_levels[21]	50	1			T29	4		T20	1		T23	1
all_levels[22]	56	1			T95	1		T98	2		T115	2
all_levels[23]	50	1			T23	1		T116	1		T111	1
all_levels[24]	48	1			T94	2		T95	1		T117	1
all_levels[25]	47	1			T11	1		T19	1		T118	1
all_levels[26]	34	1			T29	1		T119	1		T120	1
all_levels[27]	36	1			T121	1		T122	1		T123	1
all_levels[28]	28	1			T124	1		T125	4		T126	1
all_levels[29]	33	1			T119	1		T122	1		T127	1
all_levels[30]	32	1			T118	1		T95	1		T128	1
all_levels[31]	32	1			T107	1		T23	1		T95	1
all_levels[32]	32	1			T111	1		T117	1		T122	1
all_levels[33]	23	1			T23	1		T113	1		T129	1
all_levels[34]	16	1			T95	1		T130	2		T131	2
all_levels[35]	18	1			T119	1		T132	1		T133	1
all_levels[36]	30	1			T12	1		T29	1		T124	1
all_levels[37]	24	1			T93	1		T122	2		T134	1
all_levels[38]	21	1			T95	1		T119	2		T135	1
all_levels[39]	17	1			T94	1		T95	1		T136	1
all_levels[40]	24	1			T94	1		T119	1		T122	1
all_levels[41]	12	1			T137	1		T134	1		T138	1
all_levels[42]	21	1			T94	1		T93	2		T113	1
all_levels[43]	21	1			T114	1		T139	1		T140	1
all_levels[44]	13	1			T141	2		T123	1		T142	1
all_levels[45]	19	1			T143	1		T113	1		T144	1
all_levels[46]	19	1			T94	2		T140	1		T133	1
all_levels[47]	25	1			T20	1		T23	2		T113	1
all_levels[48]	6	1			T145	2		T146	1		T147	1
all_levels[49]	10	1			T145	1		T148	1		T149	1
all_levels[50]	11	1			T12	1		T29	1		T145	1
all_levels[51]	8	1			T150	1		T151	1		T152	1
all_levels[52]	7	1			T153	1		T154	1		T155	2
all_levels[53]	2	1			T156	1		T157	1		-	-
all_levels[54]	6	1			T158	1		T159	1		T160	1
all_levels[55]	2	1			T161	1		T162	1		-	-
all_levels[56]	4	1			T129	1		T115	1		T163	1
all_levels[57]	6	1			T19	1		T117	1		T161	1
all_levels[58]	9	1			T148	1		T136	1		T164	1
all_levels[59]	3	1			T165	1		T166	1		T167	1
all_levels[60]	5	1			T168	1		T169	1		T170	1
all_levels[61]	10	1			T171	1		T154	1		T172	2
all_levels[62]	4	1			T113	1		T173	1		T174	1
all_levels[63]	9	1			T145	1		T175	1		T176	1
all_levels[64]	95	1			T19	1		T20	1		T145	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22351571

1

T11

11

T12

19

T13

5

auto[1]

3986

1

T10

8

T11

1

T15

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[53] , all_levels[54] , all_levels[55] , all_levels[56] , all_levels[57]]	[auto[1]]	--	--	5
[all_levels[59] , all_levels[60]]	[auto[1]]	--	--	2
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	22204014	1			T11	9		T12	16		T13	5
all_levels[0]	auto[1]	3581	1			T10	8		T11	1		T15	1
all_levels[1]	auto[0]	140569	1			T75	2		T32	17		T46	9
all_levels[1]	auto[1]	69	1			T119	2		T125	1		T158	2
all_levels[2]	auto[0]	2147	1			T11	1		T32	7		T46	4
all_levels[2]	auto[1]	26	1			T177	2		T117	1		T178	1
all_levels[3]	auto[0]	918	1			T75	1		T46	1		T33	5
all_levels[3]	auto[1]	22	1			T91	1		T150	1		T179	1
all_levels[4]	auto[0]	581	1			T12	1		T32	4		T46	2
all_levels[4]	auto[1]	15	1			T180	1		T181	1		T182	1
all_levels[5]	auto[0]	435	1			T32	2		T46	1		T33	1
all_levels[5]	auto[1]	13	1			T94	1		T183	1		T184	1
all_levels[6]	auto[0]	328	1			T32	1		T46	2		T33	2
all_levels[6]	auto[1]	11	1			T179	1		T185	1		T172	2
all_levels[7]	auto[0]	300	1			T30	1		T32	1		T33	1
all_levels[7]	auto[1]	18	1			T94	3		T186	2		T187	1
all_levels[8]	auto[0]	223	1			T32	1		T46	1		T33	1
all_levels[8]	auto[1]	6	1			T188	1		T176	1		T189	1
all_levels[9]	auto[0]	186	1			T30	1		T33	1		T104	1
all_levels[9]	auto[1]	11	1			T30	1		T190	2		T191	1
all_levels[10]	auto[0]	156	1			T104	1		T29	1		T105	1
all_levels[10]	auto[1]	14	1			T141	4		T179	1		T192	1
all_levels[11]	auto[0]	139	1			T75	1		T106	2		T23	2
all_levels[11]	auto[1]	10	1			T193	3		T194	1		T195	1
all_levels[12]	auto[0]	132	1			T107	1		T91	1		T106	1
all_levels[12]	auto[1]	10	1			T139	1		T196	2		T184	1
all_levels[13]	auto[0]	98	1			T33	1		T108	1		T23	1
all_levels[13]	auto[1]	3	1			T197	1		T198	1		T199	1
all_levels[14]	auto[0]	83	1			T23	2		T109	1		T110	1
all_levels[14]	auto[1]	4	1			T23	1		T200	1		T201	2
all_levels[15]	auto[0]	105	1			T33	1		T91	1		T36	1
all_levels[15]	auto[1]	10	1			T188	1		T202	1		T203	1
all_levels[16]	auto[0]	71	1			T29	1		T106	1		T111	1
all_levels[16]	auto[1]	5	1			T181	2		T204	1		T205	2
all_levels[17]	auto[0]	65	1			T105	1		T112	1		T113	1
all_levels[17]	auto[1]	14	1			T206	2		T207	1		T208	1
all_levels[18]	auto[0]	69	1			T114	1		T29	1		T94	1
all_levels[18]	auto[1]	5	1			T209	1		T210	1		T211	1
all_levels[19]	auto[0]	52	1			T26	1		T33	1		T94	1
all_levels[19]	auto[1]	6	1			T26	1		T184	1		T162	1
all_levels[20]	auto[0]	53	1			T20	1		T94	1		T110	2
all_levels[20]	auto[1]	2	1			T212	1		T213	1		-	-
all_levels[21]	auto[0]	48	1			T29	4		T20	1		T23	1
all_levels[21]	auto[1]	2	1			T214	1		T215	1		-	-
all_levels[22]	auto[0]	52	1			T95	1		T98	2		T115	2
all_levels[22]	auto[1]	4	1			T216	1		T217	1		T218	1
all_levels[23]	auto[0]	44	1			T23	1		T116	1		T111	1
all_levels[23]	auto[1]	6	1			T150	1		T219	3		T147	1
all_levels[24]	auto[0]	41	1			T94	1		T95	1		T117	1
all_levels[24]	auto[1]	7	1			T94	1		T220	1		T221	1
all_levels[25]	auto[0]	38	1			T11	1		T19	1		T118	1
all_levels[25]	auto[1]	9	1			T177	1		T159	2		T222	1
all_levels[26]	auto[0]	32	1			T29	1		T119	1		T120	1
all_levels[26]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[27]	auto[0]	30	1			T121	1		T122	1		T123	1
all_levels[27]	auto[1]	6	1			T225	1		T226	2		T227	2
all_levels[28]	auto[0]	23	1			T124	1		T125	1		T126	1
all_levels[28]	auto[1]	5	1			T125	3		T228	1		T229	1
all_levels[29]	auto[0]	31	1			T119	1		T122	1		T127	1
all_levels[29]	auto[1]	2	1			T163	1		T230	1		-	-
all_levels[30]	auto[0]	26	1			T118	1		T95	1		T128	1
all_levels[30]	auto[1]	6	1			T231	1		T232	1		T233	1
all_levels[31]	auto[0]	25	1			T107	1		T23	1		T95	1
all_levels[31]	auto[1]	7	1			T234	2		T235	1		T236	3
all_levels[32]	auto[0]	28	1			T111	1		T117	1		T122	1
all_levels[32]	auto[1]	4	1			T237	1		T147	3		-	-
all_levels[33]	auto[0]	22	1			T23	1		T113	1		T129	1
all_levels[33]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[34]	auto[0]	15	1			T95	1		T130	2		T131	2
all_levels[34]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[35]	auto[0]	17	1			T119	1		T132	1		T133	1
all_levels[35]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[36]	auto[0]	25	1			T12	1		T29	1		T124	1
all_levels[36]	auto[1]	5	1			T158	3		T241	1		T242	1
all_levels[37]	auto[0]	23	1			T93	1		T122	2		T134	1
all_levels[37]	auto[1]	1	1			T165	1		-	-		-	-
all_levels[38]	auto[0]	17	1			T95	1		T119	1		T135	1
all_levels[38]	auto[1]	4	1			T119	1		T187	2		T243	1
all_levels[39]	auto[0]	17	1			T94	1		T95	1		T136	1
all_levels[40]	auto[0]	16	1			T94	1		T119	1		T122	1
all_levels[40]	auto[1]	8	1			T171	4		T244	1		T245	1
all_levels[41]	auto[0]	12	1			T137	1		T134	1		T138	1
all_levels[42]	auto[0]	20	1			T94	1		T93	1		T113	1
all_levels[42]	auto[1]	1	1			T93	1		-	-		-	-
all_levels[43]	auto[0]	17	1			T114	1		T139	1		T140	1
all_levels[43]	auto[1]	4	1			T243	4		-	-		-	-
all_levels[44]	auto[0]	12	1			T141	2		T123	1		T142	1
all_levels[44]	auto[1]	1	1			T246	1		-	-		-	-
all_levels[45]	auto[0]	14	1			T143	1		T113	1		T144	1
all_levels[45]	auto[1]	5	1			T247	2		T248	1		T204	1
all_levels[46]	auto[0]	13	1			T94	1		T140	1		T133	1
all_levels[46]	auto[1]	6	1			T94	1		T185	3		T249	2
all_levels[47]	auto[0]	17	1			T20	1		T23	1		T113	1
all_levels[47]	auto[1]	8	1			T23	1		T117	3		T250	2
all_levels[48]	auto[0]	6	1			T145	2		T146	1		T147	1
all_levels[49]	auto[0]	8	1			T145	1		T148	1		T149	1
all_levels[49]	auto[1]	2	1			T251	1		T252	1		-	-
all_levels[50]	auto[0]	10	1			T12	1		T29	1		T145	1
all_levels[50]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[51]	auto[0]	8	1			T150	1		T151	1		T152	1
all_levels[52]	auto[0]	6	1			T153	1		T154	1		T155	2
all_levels[52]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[53]	auto[0]	2	1			T156	1		T157	1		-	-
all_levels[54]	auto[0]	6	1			T158	1		T159	1		T160	1
all_levels[55]	auto[0]	2	1			T161	1		T162	1		-	-
all_levels[56]	auto[0]	4	1			T129	1		T115	1		T163	1
all_levels[57]	auto[0]	6	1			T19	1		T117	1		T161	1
all_levels[58]	auto[0]	7	1			T148	1		T136	1		T164	1
all_levels[58]	auto[1]	2	1			T255	1		T256	1		-	-
all_levels[59]	auto[0]	3	1			T165	1		T166	1		T167	1
all_levels[60]	auto[0]	5	1			T168	1		T169	1		T170	1
all_levels[61]	auto[0]	5	1			T171	1		T154	1		T172	2
all_levels[61]	auto[1]	5	1			T248	5		-	-		-	-
all_levels[62]	auto[0]	4	1			T113	1		T173	1		T174	1
all_levels[63]	auto[0]	9	1			T145	1		T175	1		T176	1
all_levels[64]	auto[0]	81	1			T19	1		T20	1		T145	2
all_levels[64]	auto[1]	14	1			T23	2		T149	2		T257	1