Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81168	1			T3	2		T4	2		T5	2
all_pins[1]	81168	1			T3	2		T4	2		T5	2
all_pins[2]	81168	1			T3	2		T4	2		T5	2
all_pins[3]	81168	1			T3	2		T4	2		T5	2
all_pins[4]	81168	1			T3	2		T4	2		T5	2
all_pins[5]	81168	1			T3	2		T4	2		T5	2
all_pins[6]	81168	1			T3	2		T4	2		T5	2
all_pins[7]	81168	1			T3	2		T4	2		T5	2
all_pins[8]	81168	1			T3	2		T4	2		T5	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	693355	1			T3	18		T4	18		T5	18
values[0x1]	37157	1			T10	1		T11	35		T15	1
transitions[0x0=>0x1]	30315	1			T11	27		T17	1		T12	10
transitions[0x1=>0x0]	30109	1			T10	1		T11	28		T15	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61735	1			T3	2		T4	2		T5	2
all_pins[0]	values[0x1]	19433	1			T11	11		T17	1		T12	7
all_pins[0]	transitions[0x0=>0x1]	18928	1			T11	9		T17	1		T12	7
all_pins[0]	transitions[0x1=>0x0]	851	1			T11	1		T75	13		T21	3
all_pins[1]	values[0x0]	79812	1			T3	2		T4	2		T5	2
all_pins[1]	values[0x1]	1356	1			T11	3		T13	1		T75	13
all_pins[1]	transitions[0x0=>0x1]	1225	1			T11	3		T13	1		T75	13
all_pins[1]	transitions[0x1=>0x0]	2038	1			T11	1		T12	1		T13	2
all_pins[2]	values[0x0]	78999	1			T3	2		T4	2		T5	2
all_pins[2]	values[0x1]	2169	1			T11	1		T12	1		T13	2
all_pins[2]	transitions[0x0=>0x1]	2109	1			T11	1		T12	1		T13	2
all_pins[2]	transitions[0x1=>0x0]	200	1			T11	2		T21	2		T18	1
all_pins[3]	values[0x0]	80908	1			T3	2		T4	2		T5	2
all_pins[3]	values[0x1]	260	1			T11	2		T21	2		T18	1
all_pins[3]	transitions[0x0=>0x1]	219	1			T11	2		T18	1		T97	1
all_pins[3]	transitions[0x1=>0x0]	294	1			T11	2		T13	1		T18	6
all_pins[4]	values[0x0]	80833	1			T3	2		T4	2		T5	2
all_pins[4]	values[0x1]	335	1			T11	2		T13	1		T21	2
all_pins[4]	transitions[0x0=>0x1]	281	1			T11	2		T21	2		T18	5
all_pins[4]	transitions[0x1=>0x0]	131	1			T21	2		T18	1		T22	2
all_pins[5]	values[0x0]	80983	1			T3	2		T4	2		T5	2
all_pins[5]	values[0x1]	185	1			T13	1		T21	2		T18	2
all_pins[5]	transitions[0x0=>0x1]	149	1			T13	1		T21	2		T18	2
all_pins[5]	transitions[0x1=>0x0]	724	1			T11	2		T12	1		T13	2
all_pins[6]	values[0x0]	80408	1			T3	2		T4	2		T5	2
all_pins[6]	values[0x1]	760	1			T11	2		T12	1		T13	2
all_pins[6]	transitions[0x0=>0x1]	714	1			T11	1		T12	1		T104	1
all_pins[6]	transitions[0x1=>0x0]	274	1			T11	1		T29	2		T21	4
all_pins[7]	values[0x0]	80848	1			T3	2		T4	2		T5	2
all_pins[7]	values[0x1]	320	1			T11	2		T13	2		T29	2
all_pins[7]	transitions[0x0=>0x1]	181	1			T11	2		T13	2		T29	2
all_pins[7]	transitions[0x1=>0x0]	12200	1			T10	1		T11	12		T15	1
all_pins[8]	values[0x0]	68829	1			T3	2		T4	2		T5	2
all_pins[8]	values[0x1]	12339	1			T10	1		T11	12		T15	1
all_pins[8]	transitions[0x0=>0x1]	6509	1			T11	7		T12	1		T13	1
all_pins[8]	transitions[0x1=>0x0]	13397	1			T11	7		T12	5		T24	12