Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5712322	1			T11	12		T15	1		T12	6
all_levels[1]	2071301	1			T12	2		T75	1		T32	22
all_levels[2]	309703	1			T12	5		T32	2		T46	10
all_levels[3]	154651	1			T26	2		T75	1		T32	7
all_levels[4]	173775	1			T11	1		T75	4		T32	1
all_levels[5]	261098	1			T75	1		T46	2		T33	4
all_levels[6]	365567	1			T12	2		T26	1		T32	1
all_levels[7]	165360	1			T75	1		T32	4		T33	4
all_levels[8]	515026	1			T30	1		T75	1		T32	7
all_levels[9]	161903	1			T75	1		T32	1		T46	1
all_levels[10]	142567	1			T32	2		T33	2		T29	2
all_levels[11]	200125	1			T75	8		T104	4		T276	8
all_levels[12]	143585	1			T26	1		T32	1		T46	1
all_levels[13]	128930	1			T26	3		T46	3		T33	56
all_levels[14]	145122	1			T26	2		T32	21		T33	4
all_levels[15]	144146	1			T32	4		T46	2		T33	9
all_levels[16]	178258	1			T75	3		T32	1		T29	3
all_levels[17]	185387	1			T32	9		T46	2		T33	9
all_levels[18]	188964	1			T32	2		T46	1		T33	6
all_levels[19]	136993	1			T33	12		T107	1		T29	2
all_levels[20]	145452	1			T75	1		T32	2		T46	15
all_levels[21]	147205	1			T30	2		T32	1		T46	4
all_levels[22]	129412	1			T75	1		T46	15		T107	2
all_levels[23]	133485	1			T46	65		T33	2		T29	4
all_levels[24]	141430	1			T32	2		T46	1		T285	2
all_levels[25]	160539	1			T30	1		T33	2		T104	10
all_levels[26]	120284	1			T32	1		T46	2		T33	2
all_levels[27]	129949	1			T26	2		T75	1		T46	1
all_levels[28]	118232	1			T75	2		T33	2		T281	2
all_levels[29]	107648	1			T30	3		T46	3		T29	6
all_levels[30]	514432	1			T32	5		T107	1		T19	2
all_levels[31]	368946	1			T33	3		T107	3		T29	1
all_levels[32]	8653563	1			T12	4		T30	3		T75	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22351571

1

T11

11

T12

19

T13

5

auto[1]

3789

1

T11

2

T15

1

T24

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5710057	1			T11	10		T12	6		T13	5
all_levels[0]	auto[1]	2265	1			T11	2		T15	1		T24	9
all_levels[1]	auto[0]	2071025	1			T12	2		T75	1		T32	22
all_levels[1]	auto[1]	276	1			T145	1		T284	11		T290	2
all_levels[2]	auto[0]	309670	1			T12	5		T32	2		T46	10
all_levels[2]	auto[1]	33	1			T114	1		T285	2		T49	2
all_levels[3]	auto[0]	154548	1			T26	2		T75	1		T32	7
all_levels[3]	auto[1]	103	1			T318	23		T368	5		T345	1
all_levels[4]	auto[0]	173758	1			T11	1		T75	4		T32	1
all_levels[4]	auto[1]	17	1			T303	1		T175	1		T324	1
all_levels[5]	auto[0]	261082	1			T75	1		T46	2		T33	4
all_levels[5]	auto[1]	16	1			T91	1		T285	2		T108	1
all_levels[6]	auto[0]	365545	1			T12	2		T26	1		T32	1
all_levels[6]	auto[1]	22	1			T281	1		T258	1		T353	1
all_levels[7]	auto[0]	165276	1			T75	1		T32	4		T33	4
all_levels[7]	auto[1]	84	1			T93	2		T96	3		T296	1
all_levels[8]	auto[0]	515008	1			T30	1		T75	1		T32	7
all_levels[8]	auto[1]	18	1			T177	1		T354	1		T422	1
all_levels[9]	auto[0]	161873	1			T75	1		T32	1		T46	1
all_levels[9]	auto[1]	30	1			T183	2		T413	1		T423	1
all_levels[10]	auto[0]	142551	1			T32	2		T33	2		T29	2
all_levels[10]	auto[1]	16	1			T200	2		T424	1		T425	1
all_levels[11]	auto[0]	200097	1			T75	8		T104	4		T276	8
all_levels[11]	auto[1]	28	1			T270	1		T117	1		T410	1
all_levels[12]	auto[0]	143570	1			T26	1		T32	1		T46	1
all_levels[12]	auto[1]	15	1			T261	1		T426	1		T427	1
all_levels[13]	auto[0]	128919	1			T26	3		T46	3		T33	56
all_levels[13]	auto[1]	11	1			T428	1		T429	1		T430	2
all_levels[14]	auto[0]	145100	1			T26	2		T32	21		T33	4
all_levels[14]	auto[1]	22	1			T200	1		T197	1		T431	1
all_levels[15]	auto[0]	144058	1			T32	4		T46	2		T33	9
all_levels[15]	auto[1]	88	1			T18	16		T92	1		T121	1
all_levels[16]	auto[0]	178239	1			T75	3		T32	1		T29	3
all_levels[16]	auto[1]	19	1			T432	1		T235	1		T203	1
all_levels[17]	auto[0]	185369	1			T32	9		T46	2		T33	9
all_levels[17]	auto[1]	18	1			T161	1		T180	1		T186	2
all_levels[18]	auto[0]	188949	1			T32	2		T46	1		T33	6
all_levels[18]	auto[1]	15	1			T413	1		T433	2		T434	3
all_levels[19]	auto[0]	136970	1			T33	12		T107	1		T29	2
all_levels[19]	auto[1]	23	1			T373	2		T269	1		T435	1
all_levels[20]	auto[0]	145421	1			T75	1		T32	2		T46	15
all_levels[20]	auto[1]	31	1			T177	2		T318	13		T436	1
all_levels[21]	auto[0]	147191	1			T30	1		T32	1		T46	4
all_levels[21]	auto[1]	14	1			T30	1		T117	1		T326	1
all_levels[22]	auto[0]	129390	1			T75	1		T46	15		T107	2
all_levels[22]	auto[1]	22	1			T150	1		T437	1		T438	1
all_levels[23]	auto[0]	133475	1			T46	65		T33	2		T29	4
all_levels[23]	auto[1]	10	1			T257	1		T184	2		T249	1
all_levels[24]	auto[0]	141400	1			T32	2		T46	1		T285	2
all_levels[24]	auto[1]	30	1			T394	1		T149	3		T439	1
all_levels[25]	auto[0]	160519	1			T30	1		T33	2		T104	10
all_levels[25]	auto[1]	20	1			T171	1		T440	1		T441	1
all_levels[26]	auto[0]	120269	1			T32	1		T46	2		T33	2
all_levels[26]	auto[1]	15	1			T51	1		T270	1		T110	2
all_levels[27]	auto[0]	129931	1			T26	2		T75	1		T46	1
all_levels[27]	auto[1]	18	1			T119	1		T134	1		T186	4
all_levels[28]	auto[0]	118227	1			T75	2		T33	2		T281	2
all_levels[28]	auto[1]	5	1			T442	1		T443	1		T444	2
all_levels[29]	auto[0]	107626	1			T30	3		T46	3		T29	6
all_levels[29]	auto[1]	22	1			T111	1		T373	3		T181	3
all_levels[30]	auto[0]	514414	1			T32	5		T107	1		T19	2
all_levels[30]	auto[1]	18	1			T445	1		T163	2		T446	1
all_levels[31]	auto[0]	368918	1			T33	3		T107	2		T29	1
all_levels[31]	auto[1]	28	1			T107	1		T121	1		T447	1
all_levels[32]	auto[0]	8653126	1			T12	4		T30	2		T75	2
all_levels[32]	auto[1]	437	1			T30	1		T91	3		T285	2