Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	730	1			T11	7		T13	7		T21	8
all_values[1]	730	1			T11	7		T13	7		T21	8
all_values[2]	730	1			T11	7		T13	7		T21	8
all_values[3]	730	1			T11	7		T13	7		T21	8
all_values[4]	730	1			T11	7		T13	7		T21	8
all_values[5]	730	1			T11	7		T13	7		T21	8
all_values[6]	730	1			T11	7		T13	7		T21	8
all_values[7]	730	1			T11	7		T13	7		T21	8
all_values[8]	730	1			T11	7		T13	7		T21	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3492

1

T11

35

T13

36

T21

42

auto[1]

3078

1

T11

28

T13

27

T21

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2145

1

T11

15

T13

24

T21

26

auto[1]

4425

1

T11

48

T13

39

T21

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3870

1

T11

33

T13

42

T21

47

auto[1]

2700

1

T11

30

T13

21

T21

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	222	1			T11	3		T13	5		T21	2
all_values[0]	auto[0]	auto[1]	auto[1]	208	1			T11	2		T13	2		T21	4
all_values[0]	auto[1]	auto[0]	auto[1]	162	1			T21	2		T23	2		T40	1
all_values[0]	auto[1]	auto[1]	auto[1]	138	1			T11	2		T38	1		T40	4
all_values[1]	auto[0]	auto[0]	auto[0]	212	1			T11	1		T21	2		T40	2
all_values[1]	auto[0]	auto[1]	auto[0]	202	1			T13	3		T21	2		T38	2
all_values[1]	auto[1]	auto[0]	auto[1]	179	1			T11	4		T13	4		T21	4
all_values[1]	auto[1]	auto[1]	auto[1]	137	1			T11	2		T99	1		T88	2
all_values[2]	auto[0]	auto[0]	auto[0]	145	1			T11	1		T13	3		T21	2
all_values[2]	auto[0]	auto[0]	auto[1]	66	1			T38	1		T99	1		T90	1
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T11	4		T13	1		T21	4
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T13	1		T40	1		T99	3
all_values[2]	auto[1]	auto[0]	auto[1]	160	1			T11	2		T13	1		T38	1
all_values[2]	auto[1]	auto[1]	auto[1]	132	1			T13	1		T21	2		T40	1
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T13	3		T21	2		T38	3
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T11	2		T21	2		T100	1
all_values[3]	auto[0]	auto[1]	auto[0]	162	1			T13	4		T21	1		T23	2
all_values[3]	auto[0]	auto[1]	auto[1]	61	1			T21	1		T40	1		T99	1
all_values[3]	auto[1]	auto[0]	auto[1]	145	1			T11	1		T21	2		T38	1
all_values[3]	auto[1]	auto[1]	auto[1]	141	1			T11	4		T40	1		T88	5
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T11	1		T21	1		T38	3
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T13	1		T23	1		T40	1
all_values[4]	auto[0]	auto[1]	auto[0]	118	1			T11	1		T13	1		T21	4
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T11	1		T13	1		T21	1
all_values[4]	auto[1]	auto[0]	auto[1]	168	1			T11	3		T13	3		T21	2
all_values[4]	auto[1]	auto[1]	auto[1]	135	1			T11	1		T13	1		T38	1
all_values[5]	auto[0]	auto[0]	auto[0]	156	1			T11	2		T13	3		T21	2
all_values[5]	auto[0]	auto[0]	auto[1]	65	1			T21	1		T40	3		T88	2
all_values[5]	auto[0]	auto[1]	auto[0]	133	1			T11	1		T21	1		T38	1
all_values[5]	auto[0]	auto[1]	auto[1]	64	1			T11	1		T13	1		T21	1
all_values[5]	auto[1]	auto[0]	auto[1]	188	1			T11	3		T13	2		T21	2
all_values[5]	auto[1]	auto[1]	auto[1]	124	1			T13	1		T21	1		T88	1
all_values[6]	auto[0]	auto[0]	auto[0]	135	1			T13	2		T21	2		T38	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T11	1		T21	2		T38	1
all_values[6]	auto[0]	auto[1]	auto[0]	140	1			T11	1		T13	1		T99	1
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T11	1		T13	1		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	177	1			T11	2		T13	1		T21	2
all_values[6]	auto[1]	auto[1]	auto[1]	125	1			T11	2		T13	2		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	159	1			T11	3		T13	3		T21	2
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T11	1		T38	1		T40	2
all_values[7]	auto[0]	auto[1]	auto[0]	124	1			T21	1		T38	1		T99	3
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T11	1		T13	1		T21	1
all_values[7]	auto[1]	auto[0]	auto[1]	161	1			T13	1		T21	2		T38	2
all_values[7]	auto[1]	auto[1]	auto[1]	142	1			T11	2		T13	2		T21	2
all_values[8]	auto[0]	auto[0]	auto[1]	255	1			T11	4		T13	3		T21	3
all_values[8]	auto[0]	auto[1]	auto[1]	189	1			T11	1		T13	2		T21	2
all_values[8]	auto[1]	auto[0]	auto[1]	145	1			T11	1		T13	1		T21	3
all_values[8]	auto[1]	auto[1]	auto[1]	141	1			T11	1		T13	1		T38	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal