Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66857207	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15494995

1

T1

12

T2

25

T3

225

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81091016	1			T1	1668		T2	1438		T3	5921
values[0x0]	611050	1			T1	6		T2	33		T3	168
values[0x1]	650136	1			T1	7		T2	19		T3	153

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46302443	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36049759

1

T1

601

T2

483

T3

2193

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	306125	1			T1	7		T2	14		T3	17
valid_sources[0x01]	291690	1			T1	12		T3	19		T7	15
valid_sources[0x02]	301866	1			T1	4		T2	8		T3	27
valid_sources[0x03]	337918	1			T1	1		T3	18		T7	12
valid_sources[0x04]	310345	1			T1	4		T2	4		T3	22
valid_sources[0x05]	289803	1			T1	5		T2	18		T3	30
valid_sources[0x06]	343637	1			T1	6		T2	13		T3	29
valid_sources[0x07]	306129	1			T1	5		T2	2		T3	23
valid_sources[0x08]	359492	1			T1	9		T3	33		T7	3
valid_sources[0x09]	348009	1			T1	3		T2	4		T3	21
valid_sources[0x0a]	321012	1			T1	5		T2	4		T3	26
valid_sources[0x0b]	317103	1			T1	6		T2	8		T3	20
valid_sources[0x0c]	284285	1			T1	1		T3	32		T7	1
valid_sources[0x0d]	290658	1			T1	5		T2	4		T3	18
valid_sources[0x0e]	294481	1			T1	11		T3	32		T7	9
valid_sources[0x0f]	322951	1			T1	7		T3	32		T7	3
valid_sources[0x10]	331732	1			T1	9		T3	25		T7	6
valid_sources[0x11]	296486	1			T1	7		T2	8		T3	28
valid_sources[0x12]	300279	1			T1	3		T2	2		T3	21
valid_sources[0x13]	319545	1			T1	7		T2	9		T3	24
valid_sources[0x14]	288851	1			T1	2		T2	5		T3	30
valid_sources[0x15]	332511	1			T1	8		T2	28		T3	36
valid_sources[0x16]	305566	1			T1	5		T3	21		T7	1
valid_sources[0x17]	301298	1			T1	8		T2	4		T3	38
valid_sources[0x18]	311646	1			T1	7		T3	31		T7	25
valid_sources[0x19]	317650	1			T1	8		T2	11		T3	11
valid_sources[0x1a]	292648	1			T1	10		T2	9		T3	32
valid_sources[0x1b]	286713	1			T1	5		T2	8		T3	21
valid_sources[0x1c]	306009	1			T1	6		T2	8		T3	25
valid_sources[0x1d]	371110	1			T1	7		T2	1		T3	29
valid_sources[0x1e]	307089	1			T1	3		T2	6		T3	28
valid_sources[0x1f]	306004	1			T1	7		T3	25		T7	5
valid_sources[0x20]	334642	1			T1	7		T2	4		T3	27
valid_sources[0x21]	311608	1			T1	3		T2	2		T3	33
valid_sources[0x22]	288048	1			T1	12		T3	28		T7	1
valid_sources[0x23]	337293	1			T1	5		T3	18		T7	5
valid_sources[0x24]	402310	1			T1	3		T2	9		T3	29
valid_sources[0x25]	317149	1			T1	5		T2	7		T3	33
valid_sources[0x26]	354627	1			T1	4		T2	8		T3	19
valid_sources[0x27]	314592	1			T1	5		T2	1		T3	13
valid_sources[0x28]	410420	1			T1	5		T2	5		T3	26
valid_sources[0x29]	315875	1			T1	5		T2	2		T3	20
valid_sources[0x2a]	378555	1			T1	5		T3	30		T7	10
valid_sources[0x2b]	509737	1			T1	9		T3	21		T7	7
valid_sources[0x2c]	338544	1			T1	8		T2	10		T3	29
valid_sources[0x2d]	288491	1			T1	5		T2	2		T3	27
valid_sources[0x2e]	315607	1			T1	10		T3	25		T7	6
valid_sources[0x2f]	301669	1			T1	9		T2	13		T3	19
valid_sources[0x30]	305059	1			T1	3		T3	31		T8	7
valid_sources[0x31]	307330	1			T1	5		T2	7		T3	28
valid_sources[0x32]	315325	1			T1	13		T3	24		T7	2
valid_sources[0x33]	314516	1			T1	9		T3	28		T7	14
valid_sources[0x34]	289842	1			T1	12		T2	3		T3	18
valid_sources[0x35]	336201	1			T1	10		T2	3		T3	26
valid_sources[0x36]	283185	1			T1	6		T2	3		T3	27
valid_sources[0x37]	300436	1			T1	5		T2	22		T3	23
valid_sources[0x38]	305309	1			T1	10		T2	7		T3	31
valid_sources[0x39]	288441	1			T1	8		T2	18		T3	24
valid_sources[0x3a]	285692	1			T1	9		T2	6		T3	24
valid_sources[0x3b]	284759	1			T1	5		T3	23		T7	3
valid_sources[0x3c]	327239	1			T1	7		T2	9		T3	27
valid_sources[0x3d]	314146	1			T1	5		T2	3		T3	19
valid_sources[0x3e]	296732	1			T1	1		T3	26		T7	15
valid_sources[0x3f]	283873	1			T1	6		T3	35		T7	7
valid_sources[0x40]	354150	1			T1	5		T2	9		T3	29
valid_sources[0x41]	290386	1			T1	2		T2	9		T3	20
valid_sources[0x42]	339967	1			T1	8		T3	24		T7	10
valid_sources[0x43]	335455	1			T1	9		T2	12		T3	24
valid_sources[0x44]	403862	1			T1	3		T2	24		T3	23
valid_sources[0x45]	316847	1			T1	8		T2	7		T3	18
valid_sources[0x46]	282620	1			T1	6		T2	6		T3	19
valid_sources[0x47]	304104	1			T1	3		T2	3		T3	18
valid_sources[0x48]	302030	1			T1	3		T2	8		T3	28
valid_sources[0x49]	330800	1			T1	7		T2	9		T3	21
valid_sources[0x4a]	288242	1			T1	15		T3	16		T7	21
valid_sources[0x4b]	464346	1			T1	1		T2	4		T3	30
valid_sources[0x4c]	370330	1			T1	5		T2	16		T3	23
valid_sources[0x4d]	299239	1			T1	5		T2	8		T3	20
valid_sources[0x4e]	357474	1			T1	6		T2	2		T3	21
valid_sources[0x4f]	429886	1			T1	1		T2	11		T3	17
valid_sources[0x50]	305432	1			T1	9		T2	2		T3	26
valid_sources[0x51]	285835	1			T1	13		T2	5		T3	23
valid_sources[0x52]	326953	1			T1	7		T2	2		T3	21
valid_sources[0x53]	320436	1			T1	1		T2	1		T3	23
valid_sources[0x54]	322395	1			T1	4		T3	19		T7	12
valid_sources[0x55]	292827	1			T1	9		T3	27		T7	10
valid_sources[0x56]	362378	1			T1	7		T2	3		T3	38
valid_sources[0x57]	338962	1			T1	3		T2	7		T3	30
valid_sources[0x58]	316836	1			T1	3		T2	5		T3	7
valid_sources[0x59]	293658	1			T1	7		T2	3		T3	23
valid_sources[0x5a]	306687	1			T1	8		T3	23		T7	2
valid_sources[0x5b]	303504	1			T1	7		T2	4		T3	26
valid_sources[0x5c]	279054	1			T1	7		T2	17		T3	17
valid_sources[0x5d]	327444	1			T1	8		T2	15		T3	26
valid_sources[0x5e]	367179	1			T1	9		T2	9		T3	41
valid_sources[0x5f]	282998	1			T1	3		T3	28		T7	2
valid_sources[0x60]	360863	1			T1	11		T3	21		T7	3
valid_sources[0x61]	322103	1			T1	5		T2	19		T3	18
valid_sources[0x62]	315105	1			T1	5		T2	17		T3	24
valid_sources[0x63]	308894	1			T1	9		T2	14		T3	20
valid_sources[0x64]	317348	1			T1	4		T2	25		T3	18
valid_sources[0x65]	347129	1			T1	3		T2	5		T3	41
valid_sources[0x66]	311519	1			T1	4		T3	36		T7	15
valid_sources[0x67]	299145	1			T1	5		T3	22		T7	27
valid_sources[0x68]	280797	1			T1	4		T2	15		T3	21
valid_sources[0x69]	290796	1			T1	7		T2	13		T3	26
valid_sources[0x6a]	428404	1			T1	9		T2	16		T3	33
valid_sources[0x6b]	382389	1			T1	5		T3	34		T7	1
valid_sources[0x6c]	318211	1			T1	3		T2	33		T3	16
valid_sources[0x6d]	324993	1			T1	4		T3	25		T7	2
valid_sources[0x6e]	301082	1			T1	8		T2	8		T3	28
valid_sources[0x6f]	288439	1			T1	3		T2	5		T3	24
valid_sources[0x70]	290357	1			T1	2		T2	1		T3	16
valid_sources[0x71]	314699	1			T1	10		T3	26		T7	10
valid_sources[0x72]	305288	1			T1	7		T2	13		T3	20
valid_sources[0x73]	391622	1			T1	4		T2	4		T3	19
valid_sources[0x74]	321098	1			T1	8		T2	9		T3	20
valid_sources[0x75]	434910	1			T1	3		T2	2		T3	32
valid_sources[0x76]	299697	1			T1	10		T3	14		T7	1
valid_sources[0x77]	295985	1			T1	5		T2	7		T3	24
valid_sources[0x78]	287776	1			T1	6		T2	2		T3	24
valid_sources[0x79]	310115	1			T1	6		T3	30		T7	1
valid_sources[0x7a]	317348	1			T1	5		T2	2		T3	37
valid_sources[0x7b]	391351	1			T1	13		T2	10		T3	32
valid_sources[0x7c]	326599	1			T1	6		T3	22		T8	17
valid_sources[0x7d]	345470	1			T1	7		T2	9		T3	28
valid_sources[0x7e]	320955	1			T1	6		T3	19		T7	1
valid_sources[0x7f]	286598	1			T1	10		T2	3		T3	25
valid_sources[0x80]	299667	1			T1	9		T3	25		T8	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14688676

1

T1

7

T2

7

T3

122

values[0x0]

all_enables

biggest_size

428192

1

T1

2

T2

13

T3

71

values[0x1]

all_enables

biggest_size

378127

1

T1

3

T2

5

T3

32