Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1024192	0	0
ctrl_rd_A	2147483647	23701	0	0
intr_enable_rd_A	2147483647	21661	0	0
ovrd_rd_A	2147483647	22548	0	0
timeout_ctrl_rd_A	2147483647	22788	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1024192	0	0
T18	492069	11673	0	0
T24	134403	4972	0	0
T25	0	17301	0	0
T33	0	18546	0	0
T34	0	2022	0	0
T35	0	26549	0	0
T36	0	14829	0	0
T37	0	3584	0	0
T38	0	13349	0	0
T39	0	7910	0	0
T40	986	0	0	0
T41	65160	0	0	0
T42	577819	0	0	0
T43	358303	0	0	0
T44	164632	0	0	0
T45	351245	0	0	0
T46	997479	0	0	0
T47	52838	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23701	0	0
T18	492069	1394	0	0
T24	134403	0	0	0
T34	0	99	0	0
T37	0	247	0	0
T39	0	874	0	0
T40	986	0	0	0
T41	65160	0	0	0
T42	577819	0	0	0
T43	358303	0	0	0
T44	164632	0	0	0
T45	351245	0	0	0
T46	997479	0	0	0
T47	52838	0	0	0
T87	0	792	0	0
T88	0	677	0	0
T89	0	429	0	0
T90	0	449	0	0
T91	0	441	0	0
T92	0	761	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21661	0	0
T11	439053	44	0	0
T12	891416	0	0	0
T17	212745	0	0	0
T18	0	1389	0	0
T19	154283	0	0	0
T21	230225	0	0	0
T23	339879	0	0	0
T31	1499	0	0	0
T32	3558	0	0	0
T34	0	128	0	0
T37	0	250	0	0
T39	0	761	0	0
T74	3222	0	0	0
T75	356743	0	0	0
T87	0	680	0	0
T88	0	440	0	0
T89	0	328	0	0
T93	0	8	0	0
T94	0	20	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22548	0	0
T18	492069	1392	0	0
T24	134403	0	0	0
T34	0	116	0	0
T37	0	216	0	0
T39	0	872	0	0
T40	986	0	0	0
T41	65160	0	0	0
T42	577819	0	0	0
T43	358303	0	0	0
T44	164632	0	0	0
T45	351245	0	0	0
T46	997479	0	0	0
T47	52838	0	0	0
T87	0	638	0	0
T88	0	531	0	0
T89	0	422	0	0
T90	0	551	0	0
T91	0	536	0	0
T92	0	752	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22788	0	0
T18	492069	1445	0	0
T24	134403	0	0	0
T34	0	93	0	0
T37	0	236	0	0
T39	0	870	0	0
T40	986	0	0	0
T41	65160	0	0	0
T42	577819	0	0	0
T43	358303	0	0	0
T44	164632	0	0	0
T45	351245	0	0	0
T46	997479	0	0	0
T47	52838	0	0	0
T87	0	685	0	0
T88	0	568	0	0
T89	0	528	0	0
T90	0	424	0	0
T91	0	447	0	0
T92	0	668	0	0