Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83631	1			T1	2		T2	11		T3	16
all_values[1]	83631	1			T1	2		T2	11		T3	16
all_values[2]	83631	1			T1	2		T2	11		T3	16
all_values[3]	83631	1			T1	2		T2	11		T3	16
all_values[4]	83631	1			T1	2		T2	11		T3	16
all_values[5]	83631	1			T1	2		T2	11		T3	16
all_values[6]	83631	1			T1	2		T2	11		T3	16
all_values[7]	83631	1			T1	2		T2	11		T3	16
all_values[8]	83631	1			T1	2		T2	11		T3	16

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

385433

1

T1

18

T2

33

T3

96

auto[1]

367246

1

T2

66

T3

48

T4

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675576

1

T1

13

T2

94

T3

112

auto[1]

77103

1

T1

5

T2

5

T3

32

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	22496	1			T11	3		T12	8		T29	6
all_values[0]	auto[0]	auto[1]	20612	1			T1	2		T4	4		T5	9
all_values[0]	auto[1]	auto[0]	23331	1			T2	7		T4	5		T5	1
all_values[0]	auto[1]	auto[1]	17192	1			T2	4		T3	16		T5	10
all_values[1]	auto[0]	auto[0]	42165	1			T1	2		T4	3		T5	20
all_values[1]	auto[0]	auto[1]	1368	1			T12	3		T29	5		T13	5
all_values[1]	auto[1]	auto[0]	38576	1			T2	11		T3	16		T4	6
all_values[1]	auto[1]	auto[1]	1522	1			T11	8		T12	5		T13	12
all_values[2]	auto[0]	auto[0]	39567	1			T1	1		T4	5		T5	10
all_values[2]	auto[0]	auto[1]	2349	1			T1	1		T5	1		T6	1
all_values[2]	auto[1]	auto[0]	39556	1			T2	11		T3	16		T4	2
all_values[2]	auto[1]	auto[1]	2159	1			T4	2		T5	5		T12	1
all_values[3]	auto[0]	auto[0]	43559	1			T1	2		T2	11		T3	16
all_values[3]	auto[0]	auto[1]	278	1			T12	3		T13	3		T19	1
all_values[3]	auto[1]	auto[0]	39513	1			T4	8		T5	9		T12	8
all_values[3]	auto[1]	auto[1]	281	1			T12	1		T18	1		T120	1
all_values[4]	auto[0]	auto[0]	40810	1			T1	2		T2	11		T3	16
all_values[4]	auto[0]	auto[1]	334	1			T13	5		T27	2		T24	16
all_values[4]	auto[1]	auto[0]	42128	1			T5	11		T11	8		T12	7
all_values[4]	auto[1]	auto[1]	359	1			T12	3		T13	1		T21	12
all_values[5]	auto[0]	auto[0]	43522	1			T1	2		T2	11		T3	16
all_values[5]	auto[0]	auto[1]	163	1			T12	2		T76	3		T113	4
all_values[5]	auto[1]	auto[0]	39781	1			T4	3		T5	9		T7	1
all_values[5]	auto[1]	auto[1]	165	1			T12	2		T38	1		T76	2
all_values[6]	auto[0]	auto[0]	41941	1			T1	2		T3	16		T4	5
all_values[6]	auto[0]	auto[1]	154	1			T12	3		T38	1		T89	2
all_values[6]	auto[1]	auto[0]	41381	1			T2	11		T4	4		T5	18
all_values[6]	auto[1]	auto[1]	155	1			T12	2		T38	1		T76	2
all_values[7]	auto[0]	auto[0]	44606	1			T1	2		T3	16		T4	4
all_values[7]	auto[0]	auto[1]	296	1			T28	1		T46	2		T19	2
all_values[7]	auto[1]	auto[0]	38411	1			T2	11		T4	5		T5	9
all_values[7]	auto[1]	auto[1]	318	1			T12	4		T13	5		T18	1
all_values[8]	auto[0]	auto[0]	25725	1			T4	5		T11	3		T12	11
all_values[8]	auto[0]	auto[1]	15488	1			T1	2		T3	16		T6	2
all_values[8]	auto[1]	auto[0]	28508	1			T2	10		T4	1		T5	5
all_values[8]	auto[1]	auto[1]	13910	1			T2	1		T4	3		T5	15