Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.10 97.65 100.00 98.38 100.00 99.44


Total tests in report: 1319
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
77.47 77.47 94.47 94.47 79.76 79.76 94.32 94.32 91.20 91.20 94.66 94.66 10.41 10.41 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_full.4046797648
82.07 4.60 94.47 0.00 79.76 0.00 94.32 0.00 91.20 0.00 94.66 0.00 38.00 27.59 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_stress_all.2046582427
86.22 4.15 97.89 3.42 91.06 11.29 97.22 2.90 93.52 2.31 96.14 1.48 41.48 3.48 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1501168067
88.11 1.89 98.39 0.50 93.18 2.12 97.47 0.25 95.83 2.31 96.14 0.00 47.62 6.14 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_stress_all.1324034371
89.45 1.34 98.39 0.00 93.18 0.00 97.47 0.00 95.83 0.00 96.14 0.00 55.66 8.04 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_stress_all.1085394641
90.58 1.13 98.39 0.00 93.18 0.00 97.47 0.00 95.83 0.00 96.14 0.00 62.45 6.80 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_stress_all.498698617
91.60 1.02 98.69 0.30 94.35 1.18 97.47 0.00 96.76 0.93 96.14 0.00 66.15 3.70 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_intr.1963974184
92.36 0.76 98.69 0.00 94.35 0.00 97.47 0.00 96.76 0.00 96.14 0.00 70.72 4.56 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_stress_all.3246905498
93.00 0.64 98.69 0.00 94.35 0.00 97.47 0.00 96.76 0.00 96.14 0.00 74.55 3.84 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.677491793
93.56 0.56 98.79 0.10 94.71 0.35 99.75 2.27 96.99 0.23 96.44 0.30 74.67 0.11 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_sec_cm.4170983116
94.11 0.55 98.99 0.20 96.35 1.65 99.75 0.00 97.92 0.93 96.44 0.00 75.21 0.54 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_intr.433199497
94.63 0.52 98.99 0.00 96.35 0.00 99.75 0.00 97.92 0.00 96.44 0.00 78.35 3.14 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_stress_all.1920672843
95.09 0.46 98.99 0.00 96.35 0.00 99.75 0.00 97.92 0.00 96.44 0.00 81.10 2.75 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_reset.3394996887
95.47 0.38 98.99 0.00 96.35 0.00 99.75 0.00 97.92 0.00 97.63 1.19 82.19 1.08 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.4145722899
95.84 0.37 98.99 0.00 96.35 0.00 99.75 0.00 97.92 0.00 97.63 0.00 84.42 2.24 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_stress_all.666632731
96.14 0.30 98.99 0.00 96.35 0.00 99.75 0.00 97.92 0.00 99.41 1.78 84.42 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1144925616
96.43 0.29 98.99 0.00 96.35 0.00 99.75 0.00 97.92 0.00 99.41 0.00 86.16 1.74 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_reset.1575194958
96.69 0.26 99.10 0.10 96.47 0.12 99.75 0.00 98.38 0.46 99.41 0.00 87.06 0.90 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3259408862
96.93 0.24 99.10 0.00 96.47 0.00 99.75 0.00 98.38 0.00 99.41 0.00 88.48 1.42 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.333178354
97.17 0.24 99.10 0.00 96.47 0.00 99.75 0.00 98.38 0.00 99.41 0.00 89.91 1.42 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_stress_all.716034345
97.36 0.20 99.10 0.00 96.47 0.00 99.75 0.00 98.38 0.00 99.41 0.00 91.08 1.17 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.1045517508
97.52 0.15 99.10 0.00 96.47 0.00 99.75 0.00 98.38 0.00 99.41 0.00 92.01 0.93 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_full.3761443553
97.66 0.14 99.10 0.00 97.18 0.71 99.75 0.00 98.38 0.00 99.41 0.00 92.17 0.16 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1714339415
97.78 0.12 99.10 0.00 97.18 0.00 99.75 0.00 98.38 0.00 99.70 0.30 92.57 0.41 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.2074190929
97.88 0.10 99.10 0.00 97.53 0.35 100.00 0.25 98.38 0.00 99.70 0.00 92.57 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_alert_test.4169518447
97.96 0.08 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 93.07 0.50 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_stress_all.2965419480
98.04 0.08 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 93.52 0.45 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_noise_filter.1100480803
98.11 0.07 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 93.95 0.43 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3425254206
98.18 0.07 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 94.36 0.41 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2599555240
98.24 0.06 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 94.72 0.36 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_stress_all.1014839286
98.29 0.06 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 95.06 0.34 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.3424812437
98.35 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 95.37 0.32 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.593539781
98.40 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.30 95.37 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.1915016437
98.44 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.66 0.29 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_stress_all.4101487754
98.49 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.94 0.27 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.1962822556
98.52 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.14 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2024612065
98.56 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.34 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_stress_all.1363333920
98.59 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.52 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_fifo_full.1329150761
98.61 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.68 0.16 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2653272845
98.64 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.84 0.16 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.465310815
98.67 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.00 0.16 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.3139691025
98.69 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.16 0.16 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/87.uart_fifo_reset.970372563
98.72 0.02 99.10 0.00 97.65 0.12 100.00 0.00 98.38 0.00 100.00 0.00 97.18 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1664256498
98.74 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.29 0.11 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_full.862612256
98.75 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.40 0.11 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.3386100238
98.77 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.52 0.11 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.454443134
98.79 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.63 0.11 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_noise_filter.3566003602
98.81 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.72 0.09 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.4096008648
98.82 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.81 0.09 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1347557991
98.84 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.90 0.09 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_fifo_reset.3921901417
98.85 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.97 0.07 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/115.uart_fifo_reset.28176609
98.86 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.04 0.07 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/119.uart_fifo_reset.2636203850
98.87 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.10 0.07 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/165.uart_fifo_reset.785331649
98.88 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.17 0.07 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.402959416
98.89 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.24 0.07 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_noise_filter.3486874809
98.90 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.31 0.07 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_fifo_reset.3521272727
98.92 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.37 0.07 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_fifo_reset.2644570134
98.92 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.42 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.884023532
98.93 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.46 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_tx_rx.2770725369
98.94 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.51 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_fifo_reset.637842672
98.95 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.55 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1245134757
98.95 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.60 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3577871097
98.96 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.65 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3583474494
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.69 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_tx_rx.1817439763
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.71 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1561848334
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.74 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.154966449
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.76 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.2618147818
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.78 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/103.uart_fifo_reset.732595481
98.99 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.80 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.4040886199
98.99 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.83 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2198759403
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.85 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2337144240
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.87 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/117.uart_fifo_reset.3422138599
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.89 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/120.uart_fifo_reset.2578939718
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.92 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/130.uart_fifo_reset.3128658330
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.94 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3199416613
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.96 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/136.uart_fifo_reset.3570843478
99.02 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.98 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.196487889
99.02 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.01 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/141.uart_fifo_reset.2970442602
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.03 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/142.uart_fifo_reset.1508114098
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.05 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/143.uart_fifo_reset.1649967389
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.07 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1615457787
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.10 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_fifo_full.2119271398
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.12 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/178.uart_fifo_reset.1073829270
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.14 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1675768646
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.16 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2225205135
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.19 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_intr.1304238591
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.21 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2593363105
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.23 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/227.uart_fifo_reset.375273891
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.25 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/231.uart_fifo_reset.241348080
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.28 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3972191783
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.30 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/254.uart_fifo_reset.3243386666
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.32 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/261.uart_fifo_reset.3667415526
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.35 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1830145400
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.37 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/278.uart_fifo_reset.413387833
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.39 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/294.uart_fifo_reset.998549447
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.41 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_fifo_reset.1920990018
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.44 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2903826293

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.93154521
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.3029168079
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.2749718969
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2259608804
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1432394736
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2943955159
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.3004956540
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2127258498
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2761691727
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3955158847
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3409182017
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1011746060
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.2575919340
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.55940754
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.4034081630
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.3107075640
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3911796059
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3593327975
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1528668996
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1974541932
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2849556892
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1080673179
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2016955577
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3454532882
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1834042292
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2043581768
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2922903756
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3582126610
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4138064255
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.4115240246
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3781332771
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.894512705
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3499998260
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.861140867
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2082979322
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1524082151
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4005514734
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2157008192
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.201660653
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1828945184
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.904116337
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3011273523
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.2224077507
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1498721045
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.435688041
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2978602899
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1557301614
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3147667713
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.83034010
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.3583778461
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1062279067
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.901446683
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.33298176
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.4099224647
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.874037611
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.3142565131
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.918475462
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3092218132
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2476113189
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3243802755
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2931642969
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2862517080
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.4237136868
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.434993108
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3618977915
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2212945736
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1932908309
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2348668785
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4213400811
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1017583453
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3793157600
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3539090532
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.830364106
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2987552932
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1020093983
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.2560851614
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2771138202
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3645272967
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3904860960
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.108051688
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1022354414
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.1562145635
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2826916330
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2830696942
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.504134160
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1574609620
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1683901508
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.665616614
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3028956686
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2788259007
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3021344075
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.4152748338
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.750858428
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1256223318
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2989487266
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2557709016
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1175661922
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1021065490
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3622157343
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3736324105
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.621004006
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.94470921
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.3459428313
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.740681263
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.1628955073
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3979434662
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.758225888
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1033536714
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1085298097
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.489826335
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3357269681
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2399705426
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2458750975
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3687725812
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.689419821
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2841291581
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2349612931
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2866812716
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.1406754643
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3283556584
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1801782273
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.859284791
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1531664559
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.617505784
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2227006805
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1798086839
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.3436840599
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.1608928928
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.518227496
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3225008988
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3394358908
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2249961015
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_loopback.2686652478
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_perf.1390885875
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_oversample.2922934007
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1409750049
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1617676406
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2959248326
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3882682039
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.1098499290
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/89.uart_fifo_reset.1399299731
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/91.uart_fifo_reset.4001599858
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2350127006
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/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3788301550
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.1268020566
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/95.uart_fifo_reset.74782280
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.2851636018
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1670884020
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.493696831
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/97.uart_fifo_reset.374765580
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2813527870
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/98.uart_fifo_reset.3570740615
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.1708436175
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/99.uart_fifo_reset.1557689842
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3354526491



Total test records in report: 1319
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_smoke.3359863886 Sep 09 06:28:11 AM UTC 24 Sep 09 06:28:13 AM UTC 24 709789404 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_tx_rx.2203132889 Sep 09 06:28:15 AM UTC 24 Sep 09 06:28:23 AM UTC 24 20154442418 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_intr.3251501707 Sep 09 06:28:34 AM UTC 24 Sep 09 06:28:46 AM UTC 24 13284113156 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2024612065 Sep 09 06:28:28 AM UTC 24 Sep 09 06:28:52 AM UTC 24 13503255608 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_full.4046797648 Sep 09 06:28:24 AM UTC 24 Sep 09 06:28:53 AM UTC 24 54469519418 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.227417852 Sep 09 06:28:53 AM UTC 24 Sep 09 06:28:56 AM UTC 24 967754198 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_loopback.2012622927 Sep 09 06:28:54 AM UTC 24 Sep 09 06:29:02 AM UTC 24 7388187060 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.154966449 Sep 09 06:28:46 AM UTC 24 Sep 09 06:29:05 AM UTC 24 4883044619 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2301553717 Sep 09 06:28:28 AM UTC 24 Sep 09 06:29:08 AM UTC 24 3535302483 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_sec_cm.4170983116 Sep 09 06:29:06 AM UTC 24 Sep 09 06:29:08 AM UTC 24 58610000 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_alert_test.4169518447 Sep 09 06:29:07 AM UTC 24 Sep 09 06:29:09 AM UTC 24 14212022 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_smoke.2596719003 Sep 09 06:29:08 AM UTC 24 Sep 09 06:29:11 AM UTC 24 629405098 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.4096008648 Sep 09 06:28:24 AM UTC 24 Sep 09 06:29:21 AM UTC 24 25919982150 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2888283588 Sep 09 06:29:23 AM UTC 24 Sep 09 06:29:27 AM UTC 24 3051568452 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1501168067 Sep 09 06:29:01 AM UTC 24 Sep 09 06:29:30 AM UTC 24 2426768136 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.1078452972 Sep 09 06:29:31 AM UTC 24 Sep 09 06:29:34 AM UTC 24 473352076 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_noise_filter.1980358965 Sep 09 06:29:21 AM UTC 24 Sep 09 06:29:35 AM UTC 24 12894880975 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_alert_test.1651778355 Sep 09 06:29:37 AM UTC 24 Sep 09 06:29:39 AM UTC 24 11636271 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_full.3761443553 Sep 09 06:29:09 AM UTC 24 Sep 09 06:29:39 AM UTC 24 40991566931 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_intr.433199497 Sep 09 06:29:12 AM UTC 24 Sep 09 06:29:39 AM UTC 24 39224243103 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_sec_cm.3983133872 Sep 09 06:29:37 AM UTC 24 Sep 09 06:29:39 AM UTC 24 210422635 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_smoke.2461224868 Sep 09 06:29:39 AM UTC 24 Sep 09 06:29:42 AM UTC 24 104729569 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_loopback.4267910770 Sep 09 06:29:35 AM UTC 24 Sep 09 06:29:42 AM UTC 24 3671470620 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_rx_oversample.1912035340 Sep 09 06:29:42 AM UTC 24 Sep 09 06:29:46 AM UTC 24 1503779523 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2398560588 Sep 09 06:29:35 AM UTC 24 Sep 09 06:29:50 AM UTC 24 3007596070 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.3424812437 Sep 09 06:29:09 AM UTC 24 Sep 09 06:29:52 AM UTC 24 91785852641 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_rx_oversample.974495875 Sep 09 06:29:11 AM UTC 24 Sep 09 06:29:52 AM UTC 24 6565730159 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.751349631 Sep 09 06:29:53 AM UTC 24 Sep 09 06:29:57 AM UTC 24 1996061675 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_noise_filter.3998203618 Sep 09 06:28:42 AM UTC 24 Sep 09 06:30:02 AM UTC 24 344244822463 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_loopback.2989515633 Sep 09 06:29:53 AM UTC 24 Sep 09 06:30:03 AM UTC 24 7335398827 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_sec_cm.976011884 Sep 09 06:30:07 AM UTC 24 Sep 09 06:30:10 AM UTC 24 207899224 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_alert_test.3462435872 Sep 09 06:30:10 AM UTC 24 Sep 09 06:30:12 AM UTC 24 30218486 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.1576955749 Sep 09 06:29:40 AM UTC 24 Sep 09 06:30:25 AM UTC 24 28214935587 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_smoke.3134905391 Sep 09 06:30:13 AM UTC 24 Sep 09 06:30:27 AM UTC 24 6214225017 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_intr.5551368 Sep 09 06:29:44 AM UTC 24 Sep 09 06:30:29 AM UTC 24 17925723800 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_tx_rx.567830649 Sep 09 06:29:39 AM UTC 24 Sep 09 06:30:29 AM UTC 24 32354756056 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.2074190929 Sep 09 06:29:51 AM UTC 24 Sep 09 06:30:34 AM UTC 24 74280632339 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_reset.3394996887 Sep 09 06:29:10 AM UTC 24 Sep 09 06:30:39 AM UTC 24 319541540268 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3259408862 Sep 09 06:30:03 AM UTC 24 Sep 09 06:30:41 AM UTC 24 33268243585 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_noise_filter.3486874809 Sep 09 06:29:47 AM UTC 24 Sep 09 06:30:44 AM UTC 24 23338933784 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_rx_oversample.704270709 Sep 09 06:30:30 AM UTC 24 Sep 09 06:30:44 AM UTC 24 2002255793 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2670274555 Sep 09 06:30:45 AM UTC 24 Sep 09 06:30:48 AM UTC 24 449044990 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.2906889038 Sep 09 06:28:48 AM UTC 24 Sep 09 06:30:51 AM UTC 24 133016126824 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_fifo_full.2551653250 Sep 09 06:30:27 AM UTC 24 Sep 09 06:30:55 AM UTC 24 107521980714 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_tx_rx.2901237104 Sep 09 06:30:24 AM UTC 24 Sep 09 06:30:56 AM UTC 24 22892941396 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.2426555416 Sep 09 06:29:48 AM UTC 24 Sep 09 06:30:59 AM UTC 24 21860298977 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.3490420662 Sep 09 06:30:42 AM UTC 24 Sep 09 06:31:00 AM UTC 24 5364058368 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_fifo_full.3616956846 Sep 09 06:29:40 AM UTC 24 Sep 09 06:31:01 AM UTC 24 22916604098 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_sec_cm.3034303713 Sep 09 06:31:01 AM UTC 24 Sep 09 06:31:03 AM UTC 24 128455807 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_stress_all.1324034371 Sep 09 06:29:03 AM UTC 24 Sep 09 06:31:03 AM UTC 24 79677226367 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_alert_test.2032325976 Sep 09 06:31:02 AM UTC 24 Sep 09 06:31:04 AM UTC 24 43326009 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_loopback.2828177722 Sep 09 06:30:48 AM UTC 24 Sep 09 06:31:07 AM UTC 24 10829881798 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2075529339 Sep 09 06:30:45 AM UTC 24 Sep 09 06:31:09 AM UTC 24 47952998298 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_noise_filter.621687487 Sep 09 06:30:40 AM UTC 24 Sep 09 06:31:10 AM UTC 24 70857611884 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_rx_oversample.3652715989 Sep 09 06:31:10 AM UTC 24 Sep 09 06:31:19 AM UTC 24 2273874310 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_smoke.2031273528 Sep 09 06:31:04 AM UTC 24 Sep 09 06:31:24 AM UTC 24 5326803869 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.1145637525 Sep 09 06:31:26 AM UTC 24 Sep 09 06:31:28 AM UTC 24 145495865 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_loopback.177428486 Sep 09 06:31:29 AM UTC 24 Sep 09 06:31:32 AM UTC 24 1059717185 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.88430836 Sep 09 06:31:25 AM UTC 24 Sep 09 06:31:35 AM UTC 24 15823472640 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_tx_rx.3197834569 Sep 09 06:31:04 AM UTC 24 Sep 09 06:31:41 AM UTC 24 9523948139 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_fifo_reset.3225663778 Sep 09 06:30:30 AM UTC 24 Sep 09 06:31:48 AM UTC 24 37864769554 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_sec_cm.2709705748 Sep 09 06:31:49 AM UTC 24 Sep 09 06:31:51 AM UTC 24 52585381 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_alert_test.951337882 Sep 09 06:31:52 AM UTC 24 Sep 09 06:31:54 AM UTC 24 61770977 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.1179012089 Sep 09 06:31:20 AM UTC 24 Sep 09 06:32:00 AM UTC 24 53237067968 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_smoke.527926629 Sep 09 06:31:54 AM UTC 24 Sep 09 06:32:00 AM UTC 24 690219371 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.915165424 Sep 09 06:30:28 AM UTC 24 Sep 09 06:32:00 AM UTC 24 186030832112 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_fifo_reset.3042909826 Sep 09 06:29:40 AM UTC 24 Sep 09 06:32:04 AM UTC 24 64765961707 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.874636960 Sep 09 06:30:58 AM UTC 24 Sep 09 06:32:10 AM UTC 24 3129929525 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_intr.3684108307 Sep 09 06:31:10 AM UTC 24 Sep 09 06:32:10 AM UTC 24 20960121308 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.1095496881 Sep 09 06:32:02 AM UTC 24 Sep 09 06:32:16 AM UTC 24 10909819123 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3230337162 Sep 09 06:31:37 AM UTC 24 Sep 09 06:32:19 AM UTC 24 14477054175 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.1534728208 Sep 09 06:32:16 AM UTC 24 Sep 09 06:32:19 AM UTC 24 4448567922 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2133904212 Sep 09 06:32:06 AM UTC 24 Sep 09 06:32:20 AM UTC 24 5909540272 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.50780737 Sep 09 06:32:20 AM UTC 24 Sep 09 06:32:24 AM UTC 24 4798562103 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_tx_rx.2420445606 Sep 09 06:32:00 AM UTC 24 Sep 09 06:32:30 AM UTC 24 30870320952 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_loopback.1394805209 Sep 09 06:32:21 AM UTC 24 Sep 09 06:32:30 AM UTC 24 5313180846 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.333178354 Sep 09 06:31:06 AM UTC 24 Sep 09 06:32:35 AM UTC 24 154638551325 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_intr.2448875337 Sep 09 06:32:11 AM UTC 24 Sep 09 06:32:49 AM UTC 24 20988700111 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_alert_test.2496122721 Sep 09 06:32:50 AM UTC 24 Sep 09 06:32:52 AM UTC 24 46128707 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_full.4000078315 Sep 09 06:31:04 AM UTC 24 Sep 09 06:32:52 AM UTC 24 29058656188 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_fifo_reset.2644570134 Sep 09 06:32:05 AM UTC 24 Sep 09 06:32:59 AM UTC 24 57936406928 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.884023532 Sep 09 06:29:28 AM UTC 24 Sep 09 06:33:02 AM UTC 24 185169049026 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_fifo_full.1648166878 Sep 09 06:32:02 AM UTC 24 Sep 09 06:33:06 AM UTC 24 65936627108 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_tx_rx.2371640308 Sep 09 06:29:09 AM UTC 24 Sep 09 06:33:09 AM UTC 24 116870990233 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_smoke.3028703246 Sep 09 06:32:53 AM UTC 24 Sep 09 06:33:17 AM UTC 24 6055681668 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_rx_oversample.4056242979 Sep 09 06:33:06 AM UTC 24 Sep 09 06:33:18 AM UTC 24 3497630647 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_reset.1575194958 Sep 09 06:31:07 AM UTC 24 Sep 09 06:33:20 AM UTC 24 144017489414 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.4220950592 Sep 09 06:33:21 AM UTC 24 Sep 09 06:33:25 AM UTC 24 1759555113 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_tx_rx.1903574789 Sep 09 06:32:53 AM UTC 24 Sep 09 06:33:35 AM UTC 24 15197126305 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_loopback.2445261284 Sep 09 06:33:26 AM UTC 24 Sep 09 06:33:37 AM UTC 24 8186991149 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_alert_test.2877597456 Sep 09 06:33:42 AM UTC 24 Sep 09 06:33:44 AM UTC 24 17202032 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_fifo_full.2092734692 Sep 09 06:33:00 AM UTC 24 Sep 09 06:33:44 AM UTC 24 17228431066 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_smoke.4233639566 Sep 09 06:33:44 AM UTC 24 Sep 09 06:33:48 AM UTC 24 308250486 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.3153191211 Sep 09 06:32:31 AM UTC 24 Sep 09 06:33:57 AM UTC 24 3050670107 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_fifo_reset.2714289619 Sep 09 06:33:02 AM UTC 24 Sep 09 06:33:59 AM UTC 24 17611214629 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_rx_oversample.581640165 Sep 09 06:33:57 AM UTC 24 Sep 09 06:34:04 AM UTC 24 4277702411 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.4145722899 Sep 09 06:33:38 AM UTC 24 Sep 09 06:34:06 AM UTC 24 2127230532 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_perf.101225008 Sep 09 06:30:51 AM UTC 24 Sep 09 06:34:12 AM UTC 24 20180177276 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_noise_filter.1161118053 Sep 09 06:32:11 AM UTC 24 Sep 09 06:34:13 AM UTC 24 51765733595 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.4193420808 Sep 09 06:34:14 AM UTC 24 Sep 09 06:34:19 AM UTC 24 2369546142 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.1010786588 Sep 09 06:34:07 AM UTC 24 Sep 09 06:34:21 AM UTC 24 7213735240 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_noise_filter.182476211 Sep 09 06:31:14 AM UTC 24 Sep 09 06:34:25 AM UTC 24 109722046709 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_loopback.3333522560 Sep 09 06:34:20 AM UTC 24 Sep 09 06:34:28 AM UTC 24 5368144172 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_tx_rx.2770725369 Sep 09 06:36:53 AM UTC 24 Sep 09 06:38:29 AM UTC 24 80967518541 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_noise_filter.2203136780 Sep 09 06:34:05 AM UTC 24 Sep 09 06:34:28 AM UTC 24 50804409121 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_alert_test.2870808827 Sep 09 06:34:28 AM UTC 24 Sep 09 06:34:30 AM UTC 24 10952509 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1694341638 Sep 09 06:33:53 AM UTC 24 Sep 09 06:34:32 AM UTC 24 12429726614 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.3962289498 Sep 09 06:33:19 AM UTC 24 Sep 09 06:34:34 AM UTC 24 116727046946 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.3599115283 Sep 09 06:33:02 AM UTC 24 Sep 09 06:34:34 AM UTC 24 30930441545 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_stress_all.498698617 Sep 09 06:31:00 AM UTC 24 Sep 09 06:34:36 AM UTC 24 603265450259 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.841241017 Sep 09 06:33:18 AM UTC 24 Sep 09 06:34:37 AM UTC 24 32532524925 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_perf.4093737313 Sep 09 06:29:58 AM UTC 24 Sep 09 06:34:37 AM UTC 24 15354168849 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_oversample.2922934007 Sep 09 06:34:38 AM UTC 24 Sep 09 06:34:41 AM UTC 24 3427521894 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1617676406 Sep 09 06:34:42 AM UTC 24 Sep 09 06:34:44 AM UTC 24 539226624 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.2052668076 Sep 09 06:34:13 AM UTC 24 Sep 09 06:34:46 AM UTC 24 77663884946 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_smoke.3683195285 Sep 09 06:34:31 AM UTC 24 Sep 09 06:34:50 AM UTC 24 5477927919 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2959248326 Sep 09 06:34:47 AM UTC 24 Sep 09 06:34:52 AM UTC 24 2892488121 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_perf.3544163194 Sep 09 06:31:32 AM UTC 24 Sep 09 06:34:54 AM UTC 24 6325605730 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_loopback.2686652478 Sep 09 06:34:51 AM UTC 24 Sep 09 06:34:54 AM UTC 24 2297091142 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_intr.705572287 Sep 09 06:34:01 AM UTC 24 Sep 09 06:34:55 AM UTC 24 21277273215 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_intr.1491405640 Sep 09 06:34:38 AM UTC 24 Sep 09 06:34:58 AM UTC 24 29795092126 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_alert_test.2840069539 Sep 09 06:34:59 AM UTC 24 Sep 09 06:35:00 AM UTC 24 32383497 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_smoke.3311407454 Sep 09 06:35:02 AM UTC 24 Sep 09 06:35:04 AM UTC 24 452998854 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_fifo_full.1017966598 Sep 09 06:34:35 AM UTC 24 Sep 09 06:35:05 AM UTC 24 44914165372 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_tx_rx.1087374220 Sep 09 06:33:45 AM UTC 24 Sep 09 06:35:17 AM UTC 24 87563681598 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.1962822556 Sep 09 06:32:20 AM UTC 24 Sep 09 06:35:19 AM UTC 24 153927194284 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_perf.3356582438 Sep 09 06:32:24 AM UTC 24 Sep 09 06:35:20 AM UTC 24 14504701166 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_tx_rx.45692465 Sep 09 06:34:32 AM UTC 24 Sep 09 06:35:32 AM UTC 24 20874824283 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_perf.1001763809 Sep 09 06:29:35 AM UTC 24 Sep 09 06:35:32 AM UTC 24 10276907258 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.3014966779 Sep 09 06:34:55 AM UTC 24 Sep 09 06:35:37 AM UTC 24 6560756496 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2479852218 Sep 09 06:35:20 AM UTC 24 Sep 09 06:35:38 AM UTC 24 5933762861 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_intr.2066784774 Sep 09 06:33:10 AM UTC 24 Sep 09 06:35:41 AM UTC 24 63960174715 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_intr.2474213404 Sep 09 06:30:35 AM UTC 24 Sep 09 06:35:42 AM UTC 24 296665051797 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_intr.4030592051 Sep 09 06:35:32 AM UTC 24 Sep 09 06:35:43 AM UTC 24 10948238850 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.807732730 Sep 09 06:34:26 AM UTC 24 Sep 09 06:35:47 AM UTC 24 4816813109 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1409750049 Sep 09 06:34:45 AM UTC 24 Sep 09 06:35:49 AM UTC 24 45529256836 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_loopback.214076975 Sep 09 06:35:43 AM UTC 24 Sep 09 06:35:50 AM UTC 24 2754026618 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_tx_rx.1817439763 Sep 09 06:35:05 AM UTC 24 Sep 09 06:35:52 AM UTC 24 74375680601 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_alert_test.2004332533 Sep 09 06:35:51 AM UTC 24 Sep 09 06:35:53 AM UTC 24 31055840 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2288605778 Sep 09 06:35:38 AM UTC 24 Sep 09 06:35:54 AM UTC 24 4600920560 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1204613259 Sep 09 06:34:36 AM UTC 24 Sep 09 06:35:55 AM UTC 24 32869345301 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.3107925363 Sep 09 06:35:42 AM UTC 24 Sep 09 06:35:57 AM UTC 24 7548690834 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_smoke.3418266131 Sep 09 06:35:53 AM UTC 24 Sep 09 06:35:59 AM UTC 24 661958846 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_fifo_reset.1921891586 Sep 09 06:34:37 AM UTC 24 Sep 09 06:35:59 AM UTC 24 128917108175 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_tx_rx.1523556255 Sep 09 06:35:54 AM UTC 24 Sep 09 06:36:08 AM UTC 24 6544828170 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.46006116 Sep 09 06:35:38 AM UTC 24 Sep 09 06:36:13 AM UTC 24 29825865921 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.665150640 Sep 09 06:36:14 AM UTC 24 Sep 09 06:36:18 AM UTC 24 1857917538 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_rx_oversample.1298862602 Sep 09 06:35:59 AM UTC 24 Sep 09 06:36:18 AM UTC 24 2305354417 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_noise_filter.1100480803 Sep 09 06:33:10 AM UTC 24 Sep 09 06:36:22 AM UTC 24 96967900876 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_fifo_reset.3173602337 Sep 09 06:35:20 AM UTC 24 Sep 09 06:36:34 AM UTC 24 35226864394 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_full.862612256 Sep 09 06:35:55 AM UTC 24 Sep 09 06:36:35 AM UTC 24 328745657329 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_loopback.2814331474 Sep 09 06:36:23 AM UTC 24 Sep 09 06:36:41 AM UTC 24 11100536054 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3425254206 Sep 09 06:35:18 AM UTC 24 Sep 09 06:36:42 AM UTC 24 89934692632 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_alert_test.2656763997 Sep 09 06:36:42 AM UTC 24 Sep 09 06:36:44 AM UTC 24 46820507 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.2618147818 Sep 09 06:36:19 AM UTC 24 Sep 09 06:36:52 AM UTC 24 12210699468 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.4202324791 Sep 09 06:36:19 AM UTC 24 Sep 09 06:36:57 AM UTC 24 130540285426 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.593539781 Sep 09 06:35:48 AM UTC 24 Sep 09 06:37:04 AM UTC 24 14964566581 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_fifo_full.917601193 Sep 09 06:33:49 AM UTC 24 Sep 09 06:37:06 AM UTC 24 133576983893 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.585267206 Sep 09 06:36:35 AM UTC 24 Sep 09 06:37:14 AM UTC 24 2279077000 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_smoke.4127441702 Sep 09 06:36:45 AM UTC 24 Sep 09 06:37:20 AM UTC 24 6071775170 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_intr.1549707036 Sep 09 06:36:00 AM UTC 24 Sep 09 06:37:24 AM UTC 24 54059741215 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.1259515929 Sep 09 06:37:21 AM UTC 24 Sep 09 06:37:24 AM UTC 24 659596505 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_stress_all.3246905498 Sep 09 06:34:56 AM UTC 24 Sep 09 06:37:27 AM UTC 24 161344964274 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.4122303166 Sep 09 06:37:25 AM UTC 24 Sep 09 06:37:28 AM UTC 24 349600900 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_loopback.1893133230 Sep 09 06:37:27 AM UTC 24 Sep 09 06:37:37 AM UTC 24 1860959194 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_fifo_reset.3833669012 Sep 09 06:37:05 AM UTC 24 Sep 09 06:37:44 AM UTC 24 12258176806 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_intr.1963974184 Sep 09 06:37:11 AM UTC 24 Sep 09 06:37:49 AM UTC 24 84451749247 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3260625297 Sep 09 06:37:07 AM UTC 24 Sep 09 06:37:51 AM UTC 24 4020869361 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_alert_test.4264944081 Sep 09 06:37:52 AM UTC 24 Sep 09 06:37:54 AM UTC 24 13219788 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2498682219 Sep 09 06:33:56 AM UTC 24 Sep 09 06:37:55 AM UTC 24 90210691417 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_smoke.2521993346 Sep 09 06:37:55 AM UTC 24 Sep 09 06:37:58 AM UTC 24 1015941948 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.514083359 Sep 09 06:36:58 AM UTC 24 Sep 09 06:38:01 AM UTC 24 18582821038 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2599555240 Sep 09 06:35:55 AM UTC 24 Sep 09 06:38:03 AM UTC 24 36544455049 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_stress_all.2046582427 Sep 09 06:31:41 AM UTC 24 Sep 09 06:38:05 AM UTC 24 342957706213 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2653272845 Sep 09 06:35:57 AM UTC 24 Sep 09 06:38:08 AM UTC 24 37141129384 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_tx_rx.2157331769 Sep 09 06:37:56 AM UTC 24 Sep 09 06:38:17 AM UTC 24 36501805970 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.4040886199 Sep 09 06:37:45 AM UTC 24 Sep 09 06:38:18 AM UTC 24 5263509575 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_rx_oversample.3544286791 Sep 09 06:38:05 AM UTC 24 Sep 09 06:38:20 AM UTC 24 5003636008 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.3484534626 Sep 09 06:38:16 AM UTC 24 Sep 09 06:38:22 AM UTC 24 1664690638 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.3529189303 Sep 09 06:38:19 AM UTC 24 Sep 09 06:38:25 AM UTC 24 3493231106 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.2096884119 Sep 09 06:37:25 AM UTC 24 Sep 09 06:38:37 AM UTC 24 101421881184 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_loopback.3964742888 Sep 09 06:38:21 AM UTC 24 Sep 09 06:38:40 AM UTC 24 8430526143 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_alert_test.1324253504 Sep 09 06:38:38 AM UTC 24 Sep 09 06:38:40 AM UTC 24 12346131 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_noise_filter.2025466212 Sep 09 06:36:09 AM UTC 24 Sep 09 06:38:42 AM UTC 24 63019566654 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_noise_filter.3958768802 Sep 09 06:37:15 AM UTC 24 Sep 09 06:38:46 AM UTC 24 111980124638 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.813794345 Sep 09 06:38:02 AM UTC 24 Sep 09 06:38:47 AM UTC 24 51292678296 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_smoke.2519186044 Sep 09 06:38:40 AM UTC 24 Sep 09 06:38:52 AM UTC 24 5318381133 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_fifo_full.3310570626 Sep 09 06:37:58 AM UTC 24 Sep 09 06:38:53 AM UTC 24 82594002324 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_stress_all.1085394641 Sep 09 06:29:36 AM UTC 24 Sep 09 06:39:02 AM UTC 24 237423092530 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_perf.1390885875 Sep 09 06:34:53 AM UTC 24 Sep 09 06:39:09 AM UTC 24 8505838572 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.2375058604 Sep 09 06:39:03 AM UTC 24 Sep 09 06:39:10 AM UTC 24 6719336216 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.2672024028 Sep 09 06:38:18 AM UTC 24 Sep 09 06:39:15 AM UTC 24 14998491092 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.846181101 Sep 09 06:37:38 AM UTC 24 Sep 09 06:39:15 AM UTC 24 323101923877 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.567070807 Sep 09 06:38:45 AM UTC 24 Sep 09 06:39:17 AM UTC 24 32478391894 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.1685758079 Sep 09 06:39:10 AM UTC 24 Sep 09 06:39:18 AM UTC 24 1077778694 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_loopback.2678596994 Sep 09 06:39:11 AM UTC 24 Sep 09 06:39:19 AM UTC 24 5434116033 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_noise_filter.3463569464 Sep 09 06:35:33 AM UTC 24 Sep 09 06:39:19 AM UTC 24 155644020616 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.809389557 Sep 09 06:35:44 AM UTC 24 Sep 09 06:39:20 AM UTC 24 62903730688 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_alert_test.4051423021 Sep 09 06:39:19 AM UTC 24 Sep 09 06:39:21 AM UTC 24 13171899 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_fifo_reset.637842672 Sep 09 06:38:04 AM UTC 24 Sep 09 06:39:22 AM UTC 24 53152263794 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_intr.1437542625 Sep 09 06:38:08 AM UTC 24 Sep 09 06:39:31 AM UTC 24 39195913945 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3630174887 Sep 09 06:38:47 AM UTC 24 Sep 09 06:39:34 AM UTC 24 4952176390 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3836068804 Sep 09 06:38:26 AM UTC 24 Sep 09 06:39:39 AM UTC 24 5218703099 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.465310815 Sep 09 06:39:08 AM UTC 24 Sep 09 06:39:40 AM UTC 24 43253131326 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_smoke.1046035609 Sep 09 06:39:19 AM UTC 24 Sep 09 06:39:40 AM UTC 24 5770074094 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1215809522 Sep 09 06:38:46 AM UTC 24 Sep 09 06:39:41 AM UTC 24 18902800883 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_rx_oversample.2571600645 Sep 09 06:39:35 AM UTC 24 Sep 09 06:39:41 AM UTC 24 2351137175 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.3757576184 Sep 09 06:39:41 AM UTC 24 Sep 09 06:39:45 AM UTC 24 1678652138 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.156503891 Sep 09 06:39:42 AM UTC 24 Sep 09 06:39:47 AM UTC 24 1764252176 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_tx_rx.3652380401 Sep 09 06:38:41 AM UTC 24 Sep 09 06:39:50 AM UTC 24 109141882157 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_loopback.4110218512 Sep 09 06:39:46 AM UTC 24 Sep 09 06:39:50 AM UTC 24 5338760344 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_noise_filter.3535822480 Sep 09 06:38:54 AM UTC 24 Sep 09 06:39:56 AM UTC 24 104289162292 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_tx_rx.631415099 Sep 09 06:39:21 AM UTC 24 Sep 09 06:39:57 AM UTC 24 27659565101 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_perf.2146294530 Sep 09 06:28:57 AM UTC 24 Sep 09 06:39:58 AM UTC 24 19804647819 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_alert_test.3318998384 Sep 09 06:39:58 AM UTC 24 Sep 09 06:39:59 AM UTC 24 11987145 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.727364854 Sep 09 06:39:17 AM UTC 24 Sep 09 06:40:02 AM UTC 24 2334821343 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_smoke.1156110877 Sep 09 06:39:59 AM UTC 24 Sep 09 06:40:03 AM UTC 24 432469591 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_fifo_full.182661235 Sep 09 06:36:55 AM UTC 24 Sep 09 06:40:09 AM UTC 24 90090925870 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1458011506 Sep 09 06:39:23 AM UTC 24 Sep 09 06:40:12 AM UTC 24 50577503303 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_noise_filter.3628266353 Sep 09 06:39:41 AM UTC 24 Sep 09 06:40:18 AM UTC 24 10422900244 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_perf.45463919 Sep 09 06:35:44 AM UTC 24 Sep 09 06:40:20 AM UTC 24 17182151252 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.677491793 Sep 09 06:30:01 AM UTC 24 Sep 09 06:40:22 AM UTC 24 80153686097 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_noise_filter.1042429539 Sep 09 06:38:09 AM UTC 24 Sep 09 06:40:30 AM UTC 24 45246985190 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_fifo_reset.2190353899 Sep 09 06:39:33 AM UTC 24 Sep 09 06:40:32 AM UTC 24 28606670492 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3946513898 Sep 09 06:40:13 AM UTC 24 Sep 09 06:40:36 AM UTC 24 5015856671 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.782546778 Sep 09 06:40:33 AM UTC 24 Sep 09 06:40:37 AM UTC 24 1295944192 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_intr.3926360659 Sep 09 06:39:40 AM UTC 24 Sep 09 06:40:39 AM UTC 24 16489380171 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_loopback.2487509335 Sep 09 06:40:38 AM UTC 24 Sep 09 06:40:40 AM UTC 24 1293547809 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_tx_rx.3808408468 Sep 09 06:40:00 AM UTC 24 Sep 09 06:40:42 AM UTC 24 66322431866 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_fifo_full.2541796697 Sep 09 06:35:06 AM UTC 24 Sep 09 06:40:43 AM UTC 24 126200980154 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_alert_test.1574302689 Sep 09 06:40:43 AM UTC 24 Sep 09 06:40:45 AM UTC 24 36310153 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_smoke.3677886071 Sep 09 06:40:45 AM UTC 24 Sep 09 06:40:48 AM UTC 24 485193229 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2232656340 Sep 09 06:39:52 AM UTC 24 Sep 09 06:40:57 AM UTC 24 10459920922 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.3386100238 Sep 09 06:40:04 AM UTC 24 Sep 09 06:40:57 AM UTC 24 30551626212 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.2460327876 Sep 09 06:29:35 AM UTC 24 Sep 09 06:40:58 AM UTC 24 119686521991 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_tx_rx.2100676027 Sep 09 06:40:49 AM UTC 24 Sep 09 06:41:02 AM UTC 24 3981199218 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3938397396 Sep 09 06:34:54 AM UTC 24 Sep 09 06:41:13 AM UTC 24 131253874595 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_intr.375312736 Sep 09 06:40:18 AM UTC 24 Sep 09 06:41:15 AM UTC 24 30059117925 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_fifo_reset.4006752467 Sep 09 06:40:10 AM UTC 24 Sep 09 06:41:18 AM UTC 24 27406861128 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_stress_all.666632731 Sep 09 06:33:40 AM UTC 24 Sep 09 06:41:19 AM UTC 24 693381520744 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_loopback.1196204317 Sep 09 06:41:20 AM UTC 24 Sep 09 06:41:22 AM UTC 24 66103919 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_intr.3110799930 Sep 09 06:41:52 AM UTC 24 Sep 09 06:42:19 AM UTC 24 15486740805 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_fifo_reset.3851622978 Sep 09 06:40:58 AM UTC 24 Sep 09 06:41:25 AM UTC 24 19261218514 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_rx_oversample.1455481832 Sep 09 06:41:00 AM UTC 24 Sep 09 06:41:28 AM UTC 24 2718585123 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.1607207243 Sep 09 06:40:41 AM UTC 24 Sep 09 06:41:29 AM UTC 24 9325133902 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.658125936 Sep 09 06:41:19 AM UTC 24 Sep 09 06:41:32 AM UTC 24 7442837707 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.390376413 Sep 09 06:40:23 AM UTC 24 Sep 09 06:41:33 AM UTC 24 73580824589 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_alert_test.2540000006 Sep 09 06:41:32 AM UTC 24 Sep 09 06:41:34 AM UTC 24 27914072 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2356150442 Sep 09 06:39:41 AM UTC 24 Sep 09 06:41:38 AM UTC 24 42848304814 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_smoke.1589302330 Sep 09 06:41:35 AM UTC 24 Sep 09 06:41:38 AM UTC 24 738908325 ps
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