Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2636

1

T1

1

T2

1

T3

1

auto[UartRx]

2636

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4578	1			T1	2		T2	2		T3	2
values[1]	40	1			T37	2		T40	1		T42	2
values[2]	53	1			T30	1		T41	1		T76	1
values[3]	59	1			T12	2		T28	1		T37	2
values[4]	79	1			T12	2		T37	2		T38	2
values[5]	46	1			T12	1		T28	1		T37	1
values[6]	72	1			T28	1		T30	1		T38	1
values[7]	60	1			T30	1		T37	1		T40	1
values[8]	54	1			T38	2		T40	2		T76	1
values[9]	81	1			T12	1		T37	1		T38	1
values[10]	97	1			T12	1		T36	2		T37	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2375	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	17	1			T40	1		T42	1		T88	2
auto[UartTx]	values[2]	14	1			T115	1		T391	1		T392	1
auto[UartTx]	values[3]	24	1			T37	1		T88	1		T92	1
auto[UartTx]	values[4]	29	1			T12	1		T37	1		T38	1
auto[UartTx]	values[5]	17	1			T12	1		T39	1		T41	1
auto[UartTx]	values[6]	29	1			T28	1		T38	1		T76	1
auto[UartTx]	values[7]	26	1			T37	1		T76	1		T115	1
auto[UartTx]	values[8]	18	1			T38	2		T40	1		T88	1
auto[UartTx]	values[9]	33	1			T37	1		T39	1		T40	1
auto[UartTx]	values[10]	32	1			T36	1		T42	1		T88	1
auto[UartRx]	values[0]	2203	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	23	1			T37	2		T42	1		T89	1
auto[UartRx]	values[2]	39	1			T30	1		T41	1		T76	1
auto[UartRx]	values[3]	35	1			T12	2		T28	1		T37	1
auto[UartRx]	values[4]	50	1			T12	1		T37	1		T38	1
auto[UartRx]	values[5]	29	1			T28	1		T37	1		T89	1
auto[UartRx]	values[6]	43	1			T30	1		T42	2		T76	3
auto[UartRx]	values[7]	34	1			T30	1		T40	1		T41	1
auto[UartRx]	values[8]	36	1			T40	1		T76	1		T88	2
auto[UartRx]	values[9]	48	1			T12	1		T38	1		T91	2
auto[UartRx]	values[10]	65	1			T12	1		T36	1		T37	1