Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1874	1			T2	1		T5	1		T9	8
auto[BaudRate115200]	1582	1			T4	1		T7	15		T8	1
auto[BaudRate230400]	1608	1			T1	1		T5	2		T7	21
auto[BaudRate128Kbps]	1552	1			T1	1		T3	1		T4	2
auto[BaudRate256Kbps]	1676	1			T5	1		T15	1		T11	1
auto[BaudRate1Mbps]	1415	1			T4	1		T5	1		T6	2
auto[BaudRate1p5Mbps]	1089	1			T4	1		T11	1		T12	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1217	1			T3	1		T43	2		T29	7
freqs[25]	1012	1			T6	2		T15	2		T13	2
freqs[48]	591	1			T50	2		T36	7		T128	10
freqs[50]	492	1			T117	16		T122	22		T97	4
freqs[100]	1046	1			T8	2		T22	2		T17	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	198	1			T45	1		T26	6		T46	1
auto[BaudRate9600]	freqs[25]	135	1			T298	1		T123	1		T98	3
auto[BaudRate9600]	freqs[48]	107	1			T50	1		T36	1		T128	3
auto[BaudRate9600]	freqs[50]	62	1			T296	3		T280	5		T112	4
auto[BaudRate9600]	freqs[100]	202	1			T292	1		T121	1		T283	4
auto[BaudRate115200]	freqs[24]	185	1			T29	3		T28	2		T23	1
auto[BaudRate115200]	freqs[25]	168	1			T13	1		T298	1		T123	2
auto[BaudRate115200]	freqs[48]	86	1			T36	1		T128	1		T303	1
auto[BaudRate115200]	freqs[50]	52	1			T117	1		T122	5		T97	1
auto[BaudRate115200]	freqs[100]	122	1			T8	1		T292	1		T313	1
auto[BaudRate230400]	freqs[24]	188	1			T29	1		T28	1		T23	1
auto[BaudRate230400]	freqs[25]	177	1			T123	2		T99	1		T130	1
auto[BaudRate230400]	freqs[48]	71	1			T36	1		T128	1		T386	1
auto[BaudRate230400]	freqs[50]	76	1			T117	5		T122	7		T97	1
auto[BaudRate230400]	freqs[100]	162	1			T8	1		T22	1		T17	2
auto[BaudRate128Kbps]	freqs[24]	161	1			T3	1		T28	1		T46	1
auto[BaudRate128Kbps]	freqs[25]	124	1			T15	1		T13	1		T123	1
auto[BaudRate128Kbps]	freqs[48]	79	1			T36	2		T128	2		T303	1
auto[BaudRate128Kbps]	freqs[50]	77	1			T117	3		T122	2		T97	1
auto[BaudRate128Kbps]	freqs[100]	121	1			T17	1		T304	2		T283	3
auto[BaudRate256Kbps]	freqs[24]	194	1			T29	1		T28	1		T26	24
auto[BaudRate256Kbps]	freqs[25]	189	1			T15	1		T98	3		T99	2
auto[BaudRate256Kbps]	freqs[48]	69	1			T128	1		T303	1		T346	2
auto[BaudRate256Kbps]	freqs[50]	69	1			T117	3		T122	3		T296	1
auto[BaudRate256Kbps]	freqs[100]	155	1			T313	1		T304	1		T121	1
auto[BaudRate1Mbps]	freqs[24]	192	1			T43	1		T29	2		T28	1
auto[BaudRate1Mbps]	freqs[25]	149	1			T6	2		T98	9		T99	1
auto[BaudRate1Mbps]	freqs[48]	81	1			T50	1		T128	1		T303	1
auto[BaudRate1Mbps]	freqs[50]	75	1			T122	2		T97	1		T296	2
auto[BaudRate1Mbps]	freqs[100]	142	1			T22	1		T288	2		T313	1
auto[BaudRate1p5Mbps]	freqs[25]	70	1			T123	1		T98	3		T393	3
auto[BaudRate1p5Mbps]	freqs[48]	98	1			T36	2		T128	1		T303	1
auto[BaudRate1p5Mbps]	freqs[50]	81	1			T117	4		T122	3		T296	4
auto[BaudRate1p5Mbps]	freqs[100]	142	1			T17	2		T304	1		T121	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded