Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_break_err_cg

Group : uart_env_pkg::uart_env_cov::rx_break_err_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_break_level	4	0	4	100.00	100	1	1	0

Summary for Variable cp_break_level

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_break_level

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	333	1			T12	4		T38	1		T76	5
all_levels[1]	21	1			T21	3		T275	2		T394	5
all_levels[2]	33	1			T24	3		T105	1		T106	2
all_levels[3]	12	1			T13	1		T105	2		T212	1