Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.39	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	15	115	88.46

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	15	115	88.46	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	23985899	1			T2	37		T3	9		T4	9
all_levels[1]	149617	1			T11	2		T43	4		T28	4
all_levels[2]	2285	1			T11	2		T116	7		T117	8
all_levels[3]	1012	1			T43	1		T116	1		T117	4
all_levels[4]	686	1			T4	2		T11	4		T12	2
all_levels[5]	443	1			T5	1		T11	2		T12	1
all_levels[6]	349	1			T4	1		T11	2		T29	2
all_levels[7]	326	1			T11	5		T118	2		T119	1
all_levels[8]	237	1			T11	6		T29	2		T119	1
all_levels[9]	197	1			T29	2		T17	1		T119	1
all_levels[10]	152	1			T11	1		T120	1		T121	1
all_levels[11]	134	1			T4	1		T11	2		T122	1
all_levels[12]	136	1			T11	1		T29	2		T14	1
all_levels[13]	134	1			T4	1		T11	1		T29	1
all_levels[14]	116	1			T4	1		T29	1		T19	1
all_levels[15]	103	1			T11	4		T19	1		T123	1
all_levels[16]	66	1			T29	1		T101	1		T104	1
all_levels[17]	70	1			T4	1		T102	2		T101	2
all_levels[18]	62	1			T4	1		T11	1		T122	1
all_levels[19]	65	1			T124	1		T125	1		T126	2
all_levels[20]	64	1			T11	1		T127	1		T104	1
all_levels[21]	47	1			T127	1		T128	1		T129	1
all_levels[22]	57	1			T120	1		T101	1		T104	1
all_levels[23]	56	1			T123	1		T130	2		T131	1
all_levels[24]	61	1			T11	1		T19	1		T102	1
all_levels[25]	33	1			T11	1		T14	1		T102	1
all_levels[26]	43	1			T11	1		T102	1		T128	1
all_levels[27]	38	1			T11	1		T122	1		T19	1
all_levels[28]	30	1			T132	1		T133	1		T134	1
all_levels[29]	42	1			T104	1		T129	2		T135	1
all_levels[30]	35	1			T29	1		T122	1		T127	1
all_levels[31]	11	1			T136	1		T137	1		T138	1
all_levels[32]	26	1			T120	1		T102	1		T136	1
all_levels[33]	24	1			T139	1		T125	2		T140	1
all_levels[34]	14	1			T141	1		T142	1		T140	1
all_levels[35]	23	1			T14	1		T46	1		T122	1
all_levels[36]	23	1			T121	1		T143	1		T125	1
all_levels[37]	19	1			T144	1		T145	2		T146	1
all_levels[38]	8	1			T29	1		T132	1		T147	1
all_levels[39]	18	1			T11	1		T144	1		T148	1
all_levels[40]	15	1			T11	1		T149	1		T150	1
all_levels[41]	9	1			T151	1		T144	1		T133	1
all_levels[42]	27	1			T120	1		T139	1		T151	1
all_levels[43]	16	1			T11	1		T14	1		T143	1
all_levels[44]	12	1			T144	1		T152	1		T153	1
all_levels[45]	10	1			T124	1		T149	1		T154	1
all_levels[46]	13	1			T42	1		T155	1		T156	1
all_levels[47]	14	1			T157	1		T158	1		T159	1
all_levels[48]	7	1			T140	1		T153	1		T160	1
all_levels[49]	21	1			T39	1		T139	1		T137	1
all_levels[50]	6	1			T155	1		T161	1		T162	1
all_levels[51]	11	1			T140	1		T155	1		T163	1
all_levels[52]	9	1			T144	1		T164	1		T159	1
all_levels[53]	15	1			T151	1		T132	1		T165	1
all_levels[54]	6	1			T166	1		T167	1		T168	1
all_levels[55]	5	1			T4	1		T139	1		T169	1
all_levels[56]	11	1			T127	1		T170	1		T171	1
all_levels[57]	13	1			T133	1		T145	1		T172	1
all_levels[58]	8	1			T173	1		T174	1		T175	1
all_levels[59]	10	1			T176	1		T177	1		T178	1
all_levels[60]	9	1			T148	1		T140	1		T179	1
all_levels[61]	10	1			T180	2		T181	1		T177	2
all_levels[62]	7	1			T182	1		T125	1		T183	1
all_levels[63]	5	1			T120	1		T142	1		T184	1
all_levels[64]	120	1			T18	1		T19	1		T120	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139358

1

T2

37

T4

16

T5

44

auto[1]

3792

1

T3

9

T4

2

T7

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	15	115	88.46	15

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[27]]	[auto[1]]	0	1	1
[all_levels[31]]	[auto[1]]	0	1	1
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[44] , all_levels[45] , all_levels[46]]	[auto[1]]	--	--	3
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51]]	[auto[1]]	--	--	2
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	23982500	1			T2	37		T4	7		T5	43
all_levels[0]	auto[1]	3399	1			T3	9		T4	2		T7	8
all_levels[1]	auto[0]	149559	1			T11	2		T43	4		T28	4
all_levels[1]	auto[1]	58	1			T102	1		T185	2		T186	1
all_levels[2]	auto[0]	2259	1			T11	2		T116	7		T117	8
all_levels[2]	auto[1]	26	1			T187	1		T188	1		T189	2
all_levels[3]	auto[0]	985	1			T43	1		T116	1		T117	4
all_levels[3]	auto[1]	27	1			T190	1		T191	1		T192	2
all_levels[4]	auto[0]	659	1			T4	2		T11	4		T12	2
all_levels[4]	auto[1]	27	1			T121	1		T187	3		T144	2
all_levels[5]	auto[0]	438	1			T5	1		T11	2		T12	1
all_levels[5]	auto[1]	5	1			T118	1		T193	1		T194	2
all_levels[6]	auto[0]	331	1			T4	1		T11	2		T29	2
all_levels[6]	auto[1]	18	1			T195	1		T190	2		T196	2
all_levels[7]	auto[0]	301	1			T11	5		T118	2		T119	1
all_levels[7]	auto[1]	25	1			T197	2		T144	2		T198	2
all_levels[8]	auto[0]	230	1			T11	6		T29	2		T119	1
all_levels[8]	auto[1]	7	1			T199	2		T200	1		T201	1
all_levels[9]	auto[0]	187	1			T29	2		T17	1		T119	1
all_levels[9]	auto[1]	10	1			T196	3		T188	1		T202	1
all_levels[10]	auto[0]	143	1			T11	1		T120	1		T121	1
all_levels[10]	auto[1]	9	1			T203	2		T204	1		T205	1
all_levels[11]	auto[0]	131	1			T4	1		T11	2		T122	1
all_levels[11]	auto[1]	3	1			T206	2		T207	1		-	-
all_levels[12]	auto[0]	120	1			T11	1		T29	2		T14	1
all_levels[12]	auto[1]	16	1			T135	2		T208	1		T209	1
all_levels[13]	auto[0]	123	1			T4	1		T11	1		T29	1
all_levels[13]	auto[1]	11	1			T102	1		T210	1		T211	1
all_levels[14]	auto[0]	104	1			T4	1		T29	1		T19	1
all_levels[14]	auto[1]	12	1			T212	1		T145	1		T188	4
all_levels[15]	auto[0]	92	1			T11	4		T19	1		T123	1
all_levels[15]	auto[1]	11	1			T213	1		T214	1		T215	2
all_levels[16]	auto[0]	64	1			T29	1		T101	1		T104	1
all_levels[16]	auto[1]	2	1			T208	1		T216	1		-	-
all_levels[17]	auto[0]	63	1			T4	1		T102	1		T101	2
all_levels[17]	auto[1]	7	1			T102	1		T217	1		T218	1
all_levels[18]	auto[0]	61	1			T4	1		T11	1		T122	1
all_levels[18]	auto[1]	1	1			T219	1		-	-		-	-
all_levels[19]	auto[0]	58	1			T124	1		T125	1		T126	2
all_levels[19]	auto[1]	7	1			T220	1		T221	2		T222	1
all_levels[20]	auto[0]	56	1			T11	1		T127	1		T104	1
all_levels[20]	auto[1]	8	1			T212	3		T205	1		T223	1
all_levels[21]	auto[0]	45	1			T127	1		T128	1		T129	1
all_levels[21]	auto[1]	2	1			T224	1		T225	1		-	-
all_levels[22]	auto[0]	53	1			T120	1		T101	1		T104	1
all_levels[22]	auto[1]	4	1			T226	2		T227	1		T228	1
all_levels[23]	auto[0]	46	1			T123	1		T130	1		T131	1
all_levels[23]	auto[1]	10	1			T130	1		T229	1		T230	1
all_levels[24]	auto[0]	51	1			T11	1		T19	1		T102	1
all_levels[24]	auto[1]	10	1			T231	1		T232	1		T226	4
all_levels[25]	auto[0]	31	1			T11	1		T14	1		T102	1
all_levels[25]	auto[1]	2	1			T128	2		-	-		-	-
all_levels[26]	auto[0]	37	1			T11	1		T102	1		T128	1
all_levels[26]	auto[1]	6	1			T233	2		T234	1		T235	1
all_levels[27]	auto[0]	38	1			T11	1		T122	1		T19	1
all_levels[28]	auto[0]	29	1			T132	1		T133	1		T134	1
all_levels[28]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[29]	auto[0]	35	1			T104	1		T129	2		T135	1
all_levels[29]	auto[1]	7	1			T237	3		T238	1		T239	2
all_levels[30]	auto[0]	32	1			T29	1		T122	1		T127	1
all_levels[30]	auto[1]	3	1			T240	2		T241	1		-	-
all_levels[31]	auto[0]	11	1			T136	1		T137	1		T138	1
all_levels[32]	auto[0]	25	1			T120	1		T102	1		T136	1
all_levels[32]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[33]	auto[0]	23	1			T139	1		T125	2		T140	1
all_levels[33]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[34]	auto[0]	13	1			T141	1		T142	1		T140	1
all_levels[34]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[35]	auto[0]	20	1			T14	1		T46	1		T122	1
all_levels[35]	auto[1]	3	1			T245	1		T246	2		-	-
all_levels[36]	auto[0]	21	1			T121	1		T143	1		T125	1
all_levels[36]	auto[1]	2	1			T247	1		T248	1		-	-
all_levels[37]	auto[0]	16	1			T144	1		T145	2		T146	1
all_levels[37]	auto[1]	3	1			T249	1		T250	2		-	-
all_levels[38]	auto[0]	8	1			T29	1		T132	1		T147	1
all_levels[39]	auto[0]	15	1			T11	1		T144	1		T148	1
all_levels[39]	auto[1]	3	1			T251	1		T252	1		T207	1
all_levels[40]	auto[0]	14	1			T11	1		T149	1		T150	1
all_levels[40]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[41]	auto[0]	9	1			T151	1		T144	1		T133	1
all_levels[42]	auto[0]	22	1			T120	1		T139	1		T151	1
all_levels[42]	auto[1]	5	1			T253	1		T254	1		T255	1
all_levels[43]	auto[0]	15	1			T11	1		T14	1		T143	1
all_levels[43]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[44]	auto[0]	12	1			T144	1		T152	1		T153	1
all_levels[45]	auto[0]	10	1			T124	1		T149	1		T154	1
all_levels[46]	auto[0]	13	1			T42	1		T155	1		T156	1
all_levels[47]	auto[0]	13	1			T157	1		T158	1		T159	1
all_levels[47]	auto[1]	1	1			T206	1		-	-		-	-
all_levels[48]	auto[0]	7	1			T140	1		T153	1		T160	1
all_levels[49]	auto[0]	16	1			T39	1		T139	1		T137	1
all_levels[49]	auto[1]	5	1			T257	4		T258	1		-	-
all_levels[50]	auto[0]	6	1			T155	1		T161	1		T162	1
all_levels[51]	auto[0]	11	1			T140	1		T155	1		T163	1
all_levels[52]	auto[0]	8	1			T144	1		T164	1		T159	1
all_levels[52]	auto[1]	1	1			T259	1		-	-		-	-
all_levels[53]	auto[0]	13	1			T151	1		T132	1		T165	1
all_levels[53]	auto[1]	2	1			T260	2		-	-		-	-
all_levels[54]	auto[0]	6	1			T166	1		T167	1		T168	1
all_levels[55]	auto[0]	5	1			T4	1		T139	1		T169	1
all_levels[56]	auto[0]	7	1			T127	1		T170	1		T171	1
all_levels[56]	auto[1]	4	1			T261	2		T262	2		-	-
all_levels[57]	auto[0]	10	1			T133	1		T145	1		T172	1
all_levels[57]	auto[1]	3	1			T263	1		T264	1		T265	1
all_levels[58]	auto[0]	7	1			T173	1		T174	1		T175	1
all_levels[58]	auto[1]	1	1			T266	1		-	-		-	-
all_levels[59]	auto[0]	8	1			T176	1		T177	1		T178	1
all_levels[59]	auto[1]	2	1			T267	2		-	-		-	-
all_levels[60]	auto[0]	9	1			T148	1		T140	1		T179	1
all_levels[61]	auto[0]	7	1			T180	1		T181	1		T177	1
all_levels[61]	auto[1]	3	1			T180	1		T177	1		T268	1
all_levels[62]	auto[0]	7	1			T182	1		T125	1		T183	1
all_levels[63]	auto[0]	5	1			T120	1		T142	1		T184	1
all_levels[64]	auto[0]	105	1			T18	1		T19	1		T120	4
all_levels[64]	auto[1]	15	1			T130	1		T269	2		T270	1