Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
1 |
7 |
87.50 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
1 |
7 |
87.50 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[7] |
0 |
1 |
1 |
|
Covered bins
| | | | | | | | | | | | |
all_levels[0] |
1436 |
1 |
|
|
T12 |
4 |
|
T27 |
8 |
|
T102 |
8 |
all_levels[1] |
529 |
1 |
|
|
T11 |
5 |
|
T12 |
4 |
|
T27 |
20 |
all_levels[2] |
351 |
1 |
|
|
T29 |
5 |
|
T13 |
12 |
|
T103 |
4 |
all_levels[3] |
298 |
1 |
|
|
T11 |
3 |
|
T13 |
5 |
|
T104 |
1 |
all_levels[4] |
188 |
1 |
|
|
T105 |
6 |
|
T106 |
6 |
|
T107 |
4 |
all_levels[5] |
45 |
1 |
|
|
T108 |
6 |
|
T109 |
6 |
|
T110 |
6 |
all_levels[6] |
32 |
1 |
|
|
T21 |
6 |
|
T111 |
4 |
|
T112 |
8 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |