Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83631	1			T1	2		T2	11		T3	16
all_pins[1]	83631	1			T1	2		T2	11		T3	16
all_pins[2]	83631	1			T1	2		T2	11		T3	16
all_pins[3]	83631	1			T1	2		T2	11		T3	16
all_pins[4]	83631	1			T1	2		T2	11		T3	16
all_pins[5]	83631	1			T1	2		T2	11		T3	16
all_pins[6]	83631	1			T1	2		T2	11		T3	16
all_pins[7]	83631	1			T1	2		T2	11		T3	16
all_pins[8]	83631	1			T1	2		T2	11		T3	16

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	715743	1			T1	18		T2	94		T3	128
values[0x1]	36936	1			T2	5		T3	16		T4	5
transitions[0x0=>0x1]	30016	1			T2	5		T3	16		T4	5
transitions[0x1=>0x0]	29835	1			T2	4		T3	15		T4	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	66372	1			T1	2		T2	7		T4	9
all_pins[0]	values[0x1]	17259	1			T2	4		T3	16		T5	10
all_pins[0]	transitions[0x0=>0x1]	16760	1			T2	4		T3	16		T5	10
all_pins[0]	transitions[0x1=>0x0]	1018	1			T11	5		T12	5		T13	12
all_pins[1]	values[0x0]	82114	1			T1	2		T2	11		T3	16
all_pins[1]	values[0x1]	1517	1			T11	8		T12	5		T13	12
all_pins[1]	transitions[0x0=>0x1]	1441	1			T11	8		T12	5		T13	12
all_pins[1]	transitions[0x1=>0x0]	2123	1			T4	2		T5	5		T12	1
all_pins[2]	values[0x0]	81432	1			T1	2		T2	11		T3	16
all_pins[2]	values[0x1]	2199	1			T4	2		T5	5		T12	1
all_pins[2]	transitions[0x0=>0x1]	2131	1			T4	2		T5	5		T12	1
all_pins[2]	transitions[0x1=>0x0]	213	1			T12	1		T18	1		T120	1
all_pins[3]	values[0x0]	83350	1			T1	2		T2	11		T3	16
all_pins[3]	values[0x1]	281	1			T12	1		T18	1		T120	1
all_pins[3]	transitions[0x0=>0x1]	226	1			T12	1		T18	1		T120	1
all_pins[3]	transitions[0x1=>0x0]	304	1			T12	3		T13	1		T21	12
all_pins[4]	values[0x0]	83272	1			T1	2		T2	11		T3	16
all_pins[4]	values[0x1]	359	1			T12	3		T13	1		T21	12
all_pins[4]	transitions[0x0=>0x1]	294	1			T12	1		T13	1		T21	12
all_pins[4]	transitions[0x1=>0x0]	143	1			T24	3		T275	2		T76	1
all_pins[5]	values[0x0]	83423	1			T1	2		T2	11		T3	16
all_pins[5]	values[0x1]	208	1			T12	2		T38	1		T24	3
all_pins[5]	transitions[0x0=>0x1]	178	1			T12	2		T38	1		T24	3
all_pins[5]	transitions[0x1=>0x0]	795	1			T5	5		T12	2		T116	1
all_pins[6]	values[0x0]	82806	1			T1	2		T2	11		T3	16
all_pins[6]	values[0x1]	825	1			T5	5		T12	2		T116	1
all_pins[6]	transitions[0x0=>0x1]	771	1			T5	5		T12	1		T116	1
all_pins[6]	transitions[0x1=>0x0]	264	1			T12	3		T13	5		T18	1
all_pins[7]	values[0x0]	83313	1			T1	2		T2	11		T3	16
all_pins[7]	values[0x1]	318	1			T12	4		T13	5		T18	1
all_pins[7]	transitions[0x0=>0x1]	191	1			T13	5		T18	1		T19	1
all_pins[7]	transitions[0x1=>0x0]	13843	1			T2	1		T4	3		T5	15
all_pins[8]	values[0x0]	69661	1			T1	2		T2	10		T3	16
all_pins[8]	values[0x1]	13970	1			T2	1		T4	3		T5	15
all_pins[8]	transitions[0x0=>0x1]	8024	1			T2	1		T4	3		T5	6
all_pins[8]	transitions[0x1=>0x0]	11132	1			T2	3		T3	15		T5	1