Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7014772	1			T3	9		T4	8		T5	36
all_levels[1]	1158275	1			T4	13		T11	5		T12	2
all_levels[2]	164437	1			T5	2		T11	1		T28	1
all_levels[3]	162871	1			T2	2		T5	1		T11	3
all_levels[4]	571282	1			T11	2		T12	16		T28	1
all_levels[5]	174018	1			T11	1		T29	13		T117	22
all_levels[6]	136090	1			T11	3		T29	1		T116	3
all_levels[7]	140876	1			T5	3		T11	4		T28	1
all_levels[8]	378060	1			T11	1		T14	4		T117	1
all_levels[9]	154943	1			T11	1		T28	1		T14	7
all_levels[10]	238112	1			T2	2		T11	1		T28	1
all_levels[11]	149323	1			T11	7		T117	9		T278	2
all_levels[12]	236878	1			T17	1		T118	1		T47	2
all_levels[13]	358641	1			T117	9		T122	7		T48	3
all_levels[14]	217732	1			T28	1		T14	2		T117	4
all_levels[15]	278482	1			T17	1		T117	2		T278	39
all_levels[16]	418794	1			T11	2		T28	1		T117	1
all_levels[17]	227098	1			T4	1		T17	2		T117	17
all_levels[18]	128888	1			T2	34		T11	3		T12	2
all_levels[19]	125830	1			T12	1		T29	5		T118	2
all_levels[20]	136685	1			T11	1		T12	1		T17	1
all_levels[21]	139474	1			T118	20		T122	11		T120	10
all_levels[22]	129643	1			T28	2		T18	2		T304	2
all_levels[23]	325743	1			T17	2		T18	1		T119	2
all_levels[24]	178901	1			T30	2		T122	2		T121	1
all_levels[25]	316567	1			T47	9		T36	79		T130	1
all_levels[26]	126403	1			T11	2		T122	2		T304	1
all_levels[27]	187793	1			T5	3		T17	2		T117	2
all_levels[28]	126680	1			T14	3		T117	7		T30	1
all_levels[29]	287270	1			T11	1		T14	2		T36	83
all_levels[30]	395923	1			T117	3		T119	17		T19	3
all_levels[31]	419881	1			T119	2		T19	1		T36	374
all_levels[32]	8936665	1			T11	23		T14	5		T17	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139358

1

T2

37

T4

16

T5

44

auto[1]

3672

1

T2

1

T3

9

T4

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7012694	1			T4	4		T5	36		T11	30
all_levels[0]	auto[1]	2078	1			T3	9		T4	4		T9	1
all_levels[1]	auto[0]	1158018	1			T4	11		T11	5		T12	2
all_levels[1]	auto[1]	257	1			T4	2		T118	2		T19	1
all_levels[2]	auto[0]	164406	1			T5	2		T11	1		T28	1
all_levels[2]	auto[1]	31	1			T102	1		T285	2		T395	1
all_levels[3]	auto[0]	162798	1			T2	2		T5	1		T11	3
all_levels[3]	auto[1]	73	1			T119	1		T122	1		T144	1
all_levels[4]	auto[0]	571265	1			T11	2		T12	16		T28	1
all_levels[4]	auto[1]	17	1			T155	1		T157	1		T396	1
all_levels[5]	auto[0]	173988	1			T11	1		T29	13		T117	22
all_levels[5]	auto[1]	30	1			T102	2		T321	1		T397	1
all_levels[6]	auto[0]	136053	1			T11	3		T29	1		T116	3
all_levels[6]	auto[1]	37	1			T314	1		T144	1		T398	1
all_levels[7]	auto[0]	140771	1			T5	3		T11	4		T28	1
all_levels[7]	auto[1]	105	1			T317	12		T21	2		T24	8
all_levels[8]	auto[0]	378051	1			T11	1		T14	4		T117	1
all_levels[8]	auto[1]	9	1			T399	1		T400	1		T401	1
all_levels[9]	auto[0]	154925	1			T11	1		T28	1		T14	7
all_levels[9]	auto[1]	18	1			T309	1		T379	1		T319	1
all_levels[10]	auto[0]	238087	1			T2	2		T11	1		T28	1
all_levels[10]	auto[1]	25	1			T14	1		T196	1		T402	1
all_levels[11]	auto[0]	149293	1			T11	7		T117	9		T278	2
all_levels[11]	auto[1]	30	1			T130	1		T128	1		T135	1
all_levels[12]	auto[0]	236846	1			T17	1		T118	1		T47	2
all_levels[12]	auto[1]	32	1			T122	1		T144	1		T199	3
all_levels[13]	auto[0]	358609	1			T117	9		T122	7		T48	2
all_levels[13]	auto[1]	32	1			T48	1		T349	1		T310	1
all_levels[14]	auto[0]	217701	1			T28	1		T14	2		T117	4
all_levels[14]	auto[1]	31	1			T199	2		T403	1		T404	1
all_levels[15]	auto[0]	278420	1			T17	1		T117	2		T278	39
all_levels[15]	auto[1]	62	1			T106	14		T89	2		T310	1
all_levels[16]	auto[0]	418778	1			T11	2		T28	1		T117	1
all_levels[16]	auto[1]	16	1			T42	1		T196	1		T405	1
all_levels[17]	auto[0]	227070	1			T4	1		T17	2		T117	17
all_levels[17]	auto[1]	28	1			T197	2		T406	1		T165	3
all_levels[18]	auto[0]	128877	1			T2	33		T11	3		T12	2
all_levels[18]	auto[1]	11	1			T2	1		T407	1		T224	1
all_levels[19]	auto[0]	125816	1			T12	1		T29	4		T118	2
all_levels[19]	auto[1]	14	1			T29	1		T112	1		T408	1
all_levels[20]	auto[0]	136665	1			T11	1		T12	1		T17	1
all_levels[20]	auto[1]	20	1			T387	1		T316	1		T409	1
all_levels[21]	auto[0]	139448	1			T118	19		T122	11		T120	10
all_levels[21]	auto[1]	26	1			T118	1		T410	1		T186	2
all_levels[22]	auto[0]	129619	1			T28	2		T18	2		T304	2
all_levels[22]	auto[1]	24	1			T305	1		T306	1		T411	1
all_levels[23]	auto[0]	325730	1			T17	2		T18	1		T119	2
all_levels[23]	auto[1]	13	1			T378	1		T144	1		T412	2
all_levels[24]	auto[0]	178887	1			T30	2		T122	2		T121	1
all_levels[24]	auto[1]	14	1			T191	1		T210	1		T146	1
all_levels[25]	auto[0]	316535	1			T47	9		T36	79		T130	1
all_levels[25]	auto[1]	32	1			T109	1		T269	1		T145	1
all_levels[26]	auto[0]	126393	1			T11	2		T122	2		T304	1
all_levels[26]	auto[1]	10	1			T171	1		T413	1		T178	1
all_levels[27]	auto[0]	187766	1			T5	2		T17	2		T117	2
all_levels[27]	auto[1]	27	1			T5	1		T307	1		T269	1
all_levels[28]	auto[0]	126669	1			T14	3		T117	7		T30	1
all_levels[28]	auto[1]	11	1			T315	2		T135	1		T212	2
all_levels[29]	auto[0]	287253	1			T11	1		T14	2		T36	83
all_levels[29]	auto[1]	17	1			T186	1		T146	1		T414	2
all_levels[30]	auto[0]	395906	1			T117	3		T119	17		T19	3
all_levels[30]	auto[1]	17	1			T310	4		T415	1		T210	1
all_levels[31]	auto[0]	419867	1			T119	2		T19	1		T36	374
all_levels[31]	auto[1]	14	1			T130	1		T187	3		T416	1
all_levels[32]	auto[0]	8936154	1			T11	23		T14	5		T17	2
all_levels[32]	auto[1]	511	1			T117	1		T120	1		T102	3