Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	711	1			T12	7		T38	7		T76	7
all_values[1]	711	1			T12	7		T38	7		T76	7
all_values[2]	711	1			T12	7		T38	7		T76	7
all_values[3]	711	1			T12	7		T38	7		T76	7
all_values[4]	711	1			T12	7		T38	7		T76	7
all_values[5]	711	1			T12	7		T38	7		T76	7
all_values[6]	711	1			T12	7		T38	7		T76	7
all_values[7]	711	1			T12	7		T38	7		T76	7
all_values[8]	711	1			T12	7		T38	7		T76	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3459

1

T12

36

T38

34

T76

27

auto[1]

2940

1

T12

27

T38

29

T76

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2074

1

T12

16

T38

23

T76

19

auto[1]

4325

1

T12

47

T38

40

T76

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3757

1

T12

32

T38

37

T76

30

auto[1]

2642

1

T12

31

T38

26

T76

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	217	1			T12	2		T38	3		T89	4
all_values[0]	auto[0]	auto[1]	auto[1]	202	1			T12	1		T38	2		T76	4
all_values[0]	auto[1]	auto[0]	auto[1]	161	1			T12	4		T76	1		T89	1
all_values[0]	auto[1]	auto[1]	auto[1]	131	1			T38	2		T76	2		T89	1
all_values[1]	auto[0]	auto[0]	auto[0]	230	1			T12	1		T38	3		T76	3
all_values[1]	auto[0]	auto[1]	auto[0]	198	1			T12	2		T38	3		T76	2
all_values[1]	auto[1]	auto[0]	auto[1]	158	1			T12	3		T38	1		T76	1
all_values[1]	auto[1]	auto[1]	auto[1]	125	1			T12	1		T76	1		T113	1
all_values[2]	auto[0]	auto[0]	auto[0]	130	1			T12	1		T38	2		T76	1
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T12	1		T38	1		T89	1
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T12	1		T38	1		T76	1
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T12	1		T89	1		T114	1
all_values[2]	auto[1]	auto[0]	auto[1]	179	1			T12	3		T38	2		T76	3
all_values[2]	auto[1]	auto[1]	auto[1]	140	1			T38	1		T76	2		T113	3
all_values[3]	auto[0]	auto[0]	auto[0]	133	1			T12	3		T38	2		T113	3
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T12	2		T38	1		T89	1
all_values[3]	auto[0]	auto[1]	auto[0]	142	1			T38	1		T76	2		T113	4
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T76	1		T89	1		T113	1
all_values[3]	auto[1]	auto[0]	auto[1]	162	1			T12	1		T38	2		T76	1
all_values[3]	auto[1]	auto[1]	auto[1]	133	1			T12	1		T38	1		T76	3
all_values[4]	auto[0]	auto[0]	auto[0]	182	1			T12	2		T76	2		T89	4
all_values[4]	auto[0]	auto[0]	auto[1]	51	1			T113	1		T115	2		T114	1
all_values[4]	auto[0]	auto[1]	auto[0]	110	1			T12	1		T38	1		T113	1
all_values[4]	auto[0]	auto[1]	auto[1]	65	1			T12	1		T38	1		T76	1
all_values[4]	auto[1]	auto[0]	auto[1]	163	1			T12	1		T38	2		T76	1
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T12	2		T38	3		T76	3
all_values[5]	auto[0]	auto[0]	auto[0]	152	1			T38	1		T76	1		T89	3
all_values[5]	auto[0]	auto[0]	auto[1]	62	1			T76	1		T113	1		T91	1
all_values[5]	auto[0]	auto[1]	auto[0]	117	1			T12	1		T38	4		T89	2
all_values[5]	auto[0]	auto[1]	auto[1]	86	1			T12	2		T89	1		T112	3
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T12	3		T38	1		T76	4
all_values[5]	auto[1]	auto[1]	auto[1]	120	1			T12	1		T38	1		T76	1
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T12	1		T38	1		T76	1
all_values[6]	auto[0]	auto[0]	auto[1]	60	1			T12	2		T89	1		T113	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T12	1		T38	3		T76	2
all_values[6]	auto[0]	auto[1]	auto[1]	69	1			T76	1		T112	2		T115	1
all_values[6]	auto[1]	auto[0]	auto[1]	164	1			T12	1		T38	2		T89	2
all_values[6]	auto[1]	auto[1]	auto[1]	125	1			T12	2		T38	1		T76	3
all_values[7]	auto[0]	auto[0]	auto[0]	147	1			T12	1		T38	1		T76	3
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T38	1		T89	2		T113	1
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T12	1		T76	1		T89	2
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T12	1		T38	2		T89	2
all_values[7]	auto[1]	auto[0]	auto[1]	160	1			T12	1		T38	1		T76	3
all_values[7]	auto[1]	auto[1]	auto[1]	120	1			T12	3		T38	2		T113	3
all_values[8]	auto[0]	auto[0]	auto[1]	222	1			T12	1		T38	3		T76	1
all_values[8]	auto[0]	auto[1]	auto[1]	202	1			T12	2		T76	2		T89	3
all_values[8]	auto[1]	auto[0]	auto[1]	163	1			T12	2		T38	4		T89	3
all_values[8]	auto[1]	auto[1]	auto[1]	124	1			T12	2		T76	4		T113	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal