Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	73452	1			T1	2		T2	2		T3	1
all_values[1]	73452	1			T1	2		T2	2		T3	1
all_values[2]	73452	1			T1	2		T2	2		T3	1
all_values[3]	73452	1			T1	2		T2	2		T3	1
all_values[4]	73452	1			T1	2		T2	2		T3	1
all_values[5]	73452	1			T1	2		T2	2		T3	1
all_values[6]	73452	1			T1	2		T2	2		T3	1
all_values[7]	73452	1			T1	2		T2	2		T3	1
all_values[8]	73452	1			T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329679

1

T1

18

T2

18

T3

4

auto[1]

331389

1

T3

5

T7

4

T11

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

591812

1

T1

13

T2

13

T3

7

auto[1]

69256

1

T1

5

T2

5

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	19617	1			T11	3		T13	9		T17	4
all_values[0]	auto[0]	auto[1]	17549	1			T1	2		T2	2		T5	2
all_values[0]	auto[1]	auto[0]	20656	1			T13	7		T37	5		T42	1
all_values[0]	auto[1]	auto[1]	15630	1			T3	1		T7	1		T11	3
all_values[1]	auto[0]	auto[0]	34244	1			T1	2		T2	2		T5	2
all_values[1]	auto[0]	auto[1]	1430	1			T19	2		T20	3		T18	14
all_values[1]	auto[1]	auto[0]	36261	1			T3	1		T11	3		T13	65
all_values[1]	auto[1]	auto[1]	1517	1			T13	2		T19	3		T18	9
all_values[2]	auto[0]	auto[0]	35353	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2414	1			T1	1		T2	1		T5	1
all_values[2]	auto[1]	auto[0]	33608	1			T11	3		T12	2		T24	1
all_values[2]	auto[1]	auto[1]	2077	1			T12	1		T21	2		T17	2
all_values[3]	auto[0]	auto[0]	34447	1			T1	2		T2	2		T5	2
all_values[3]	auto[0]	auto[1]	279	1			T13	1		T19	5		T18	1
all_values[3]	auto[1]	auto[0]	38419	1			T3	1		T11	4		T12	2
all_values[3]	auto[1]	auto[1]	307	1			T11	2		T19	3		T18	1
all_values[4]	auto[0]	auto[0]	39340	1			T1	2		T2	2		T3	1
all_values[4]	auto[0]	auto[1]	421	1			T13	6		T19	3		T20	5
all_values[4]	auto[1]	auto[0]	33318	1			T7	1		T11	3		T24	1
all_values[4]	auto[1]	auto[1]	373	1			T19	1		T18	5		T30	3
all_values[5]	auto[0]	auto[0]	35132	1			T1	2		T2	2		T5	2
all_values[5]	auto[0]	auto[1]	177	1			T19	3		T30	2		T34	1
all_values[5]	auto[1]	auto[0]	37973	1			T3	1		T7	1		T11	3
all_values[5]	auto[1]	auto[1]	170	1			T19	4		T34	1		T66	1
all_values[6]	auto[0]	auto[0]	36203	1			T1	2		T2	2		T3	1
all_values[6]	auto[0]	auto[1]	185	1			T30	2		T66	3		T36	2
all_values[6]	auto[1]	auto[0]	36895	1			T11	3		T12	2		T13	33
all_values[6]	auto[1]	auto[1]	169	1			T19	1		T34	1		T66	2
all_values[7]	auto[0]	auto[0]	35352	1			T1	2		T2	2		T3	1
all_values[7]	auto[0]	auto[1]	381	1			T11	2		T13	4		T19	4
all_values[7]	auto[1]	auto[0]	37392	1			T11	3		T12	2		T13	33
all_values[7]	auto[1]	auto[1]	327	1			T19	1		T30	4		T116	2
all_values[8]	auto[0]	auto[0]	23649	1			T11	3		T13	13		T19	74
all_values[8]	auto[0]	auto[1]	13506	1			T1	2		T2	2		T5	2
all_values[8]	auto[1]	auto[0]	23953	1			T13	15		T17	4		T83	10
all_values[8]	auto[1]	auto[1]	12344	1			T3	1		T7	1		T11	3