Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total tests in report: 1318
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
75.86 75.86 94.27 94.27 77.41 77.41 94.07 94.07 90.74 90.74 94.36 94.36 4.34 4.34 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_loopback.1067029679
81.11 5.24 97.69 3.42 90.00 12.59 97.22 3.16 92.82 2.08 97.03 2.67 11.88 7.54 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2911735312
84.37 3.27 97.69 0.00 90.00 0.00 97.22 0.00 92.82 0.00 97.03 0.00 31.47 19.60 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_stress_all.821746638
86.41 2.04 97.69 0.00 90.00 0.00 97.22 0.00 92.82 0.00 97.03 0.00 43.71 12.24 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_stress_all.1162157750
88.18 1.77 97.99 0.30 91.76 1.76 97.22 0.00 94.21 1.39 97.33 0.30 50.58 6.86 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_tx_rx.2816969887
89.55 1.37 97.99 0.00 91.76 0.00 97.22 0.00 94.21 0.00 97.33 0.00 58.77 8.20 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_stress_all.1368692866
90.75 1.20 98.49 0.50 94.71 2.94 97.22 0.00 96.30 2.08 97.33 0.00 60.47 1.69 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_intr.2804810282
91.76 1.01 98.49 0.00 94.71 0.00 97.22 0.00 96.30 0.00 97.33 0.00 66.54 6.07 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_stress_all.2352246946
92.57 0.80 98.99 0.50 95.88 1.18 97.22 0.00 98.15 1.85 97.33 0.00 67.83 1.29 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.296909277
93.19 0.62 98.99 0.00 95.88 0.00 97.22 0.00 98.15 0.00 97.33 0.00 71.57 3.75 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_full.3825874130
93.80 0.60 99.10 0.10 96.24 0.35 99.75 2.53 98.38 0.23 97.63 0.30 71.69 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_sec_cm.1169502644
94.32 0.52 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 97.63 0.00 74.83 3.14 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_stress_all.813459436
94.79 0.47 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 97.63 0.00 77.67 2.84 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_tx_rx.3816913803
95.26 0.47 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 97.63 0.00 80.47 2.80 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.113871231
95.61 0.35 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 97.63 0.00 82.55 2.08 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.1661127755
95.90 0.30 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 99.41 1.78 82.55 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2028940423
96.20 0.29 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 99.41 0.00 84.31 1.76 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.1739937843
96.45 0.26 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 99.41 0.00 85.84 1.54 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.846510331
96.67 0.22 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 99.41 0.00 87.18 1.33 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_tx_rx.3407993449
96.86 0.18 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 99.41 0.00 88.28 1.11 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_intr.81533557
97.02 0.16 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 99.41 0.00 89.25 0.97 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3313833939
97.17 0.15 99.10 0.00 96.24 0.00 99.75 0.00 98.38 0.00 99.41 0.00 90.16 0.90 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.76193385
97.31 0.14 99.10 0.00 96.94 0.71 99.75 0.00 98.38 0.00 99.41 0.00 90.31 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2496747258
97.46 0.14 99.10 0.00 96.94 0.00 99.75 0.00 98.38 0.00 99.41 0.00 91.17 0.86 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_stress_all.1394020518
97.60 0.14 99.10 0.00 96.94 0.00 99.75 0.00 98.38 0.00 99.41 0.00 92.03 0.86 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_fifo_full.4174579569
97.72 0.12 99.10 0.00 97.06 0.12 99.75 0.00 98.38 0.00 99.41 0.00 92.66 0.63 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.172325477
97.84 0.11 99.10 0.00 97.06 0.00 99.75 0.00 98.38 0.00 99.41 0.00 93.34 0.68 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_fifo_reset.1037420152
97.94 0.10 99.10 0.00 97.41 0.35 100.00 0.25 98.38 0.00 99.41 0.00 93.34 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_alert_test.2315328042
98.02 0.08 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 99.70 0.30 93.54 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1389694527
98.09 0.07 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 99.70 0.00 93.95 0.41 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_intr.2231841740
98.15 0.06 99.10 0.00 97.41 0.00 100.00 0.00 98.38 0.00 99.70 0.00 94.33 0.38 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_stress_all.199986610
98.21 0.06 99.10 0.00 97.53 0.12 100.00 0.00 98.38 0.00 99.70 0.00 94.58 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.211426004
98.28 0.06 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 94.94 0.36 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_stress_all.3861265763
98.34 0.06 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 99.70 0.00 95.30 0.36 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_stress_all.1149655218
98.38 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.30 95.30 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1734590085
98.43 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.57 0.27 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_fifo_reset.1195666791
98.48 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.85 0.27 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_fifo_reset.2738733605
98.52 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.12 0.27 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_stress_all.2569710815
98.57 0.05 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.39 0.27 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.4276417168
98.60 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.59 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_fifo_full.5348442
98.63 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.79 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.1013087180
98.66 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.97 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2878635417
98.69 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.13 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_fifo_reset.4027615631
98.72 0.03 99.10 0.00 97.53 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.29 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.3172334036
98.74 0.02 99.10 0.00 97.65 0.12 100.00 0.00 98.38 0.00 100.00 0.00 97.31 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3780590753
98.76 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.45 0.14 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_fifo_reset.2208711962
98.78 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.56 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_noise_filter.2148751649
98.80 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.67 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_fifo_full.2901456542
98.82 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.79 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/168.uart_fifo_reset.714677080
98.84 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.90 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_tx_rx.2212823699
98.85 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.99 0.09 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2871121799
98.87 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.08 0.09 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/115.uart_fifo_reset.3494883580
98.88 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.17 0.09 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2477975399
98.90 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.26 0.09 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/82.uart_fifo_reset.2961103070
98.91 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.33 0.07 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2531132550
98.92 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.40 0.07 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3404615830
98.93 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.46 0.07 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/191.uart_fifo_reset.128870887
98.94 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.53 0.07 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3758106137
98.95 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.60 0.07 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_stress_all.1819218265
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.67 0.07 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/90.uart_fifo_reset.3135038388
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.71 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_perf.1047738221
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/142.uart_fifo_reset.2978880015
98.99 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.80 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_tx_rx.3717713515
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.85 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_fifo_reset.3300626836
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.89 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.126456118
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.94 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_stress_all.3335636815
99.02 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.98 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1295600972
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.03 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_noise_filter.211268752
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.05 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3825044493
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.07 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.829793041
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.10 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/100.uart_fifo_reset.143931105
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.12 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/103.uart_fifo_reset.3308003215
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.14 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/114.uart_fifo_reset.2715803682
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.16 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/122.uart_fifo_reset.1712430147
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.19 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_fifo_reset.3998343853
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.21 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3684847364
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.23 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/140.uart_fifo_reset.953398808
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.25 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/146.uart_fifo_reset.2943622176
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.28 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_intr.409412343
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.30 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/154.uart_fifo_reset.3910196324
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.32 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/155.uart_fifo_reset.864411741
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.35 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_fifo_reset.2578067712
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.37 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2910300246
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.39 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/242.uart_fifo_reset.4223784887
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.41 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/264.uart_fifo_reset.2854662603
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.44 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1822672971
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.46 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1447529756
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.48 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/296.uart_fifo_reset.2755057647
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.50 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_fifo_reset.2116598453
99.11 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.53 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/52.uart_fifo_reset.2194945518
99.11 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.55 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1326736047
99.12 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.57 0.02 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/76.uart_fifo_reset.1099708740

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.169223878
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2004830552
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3788194458
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3994919328
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3658486529
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3670331861
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.4245097550
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.928394440
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.1745434365
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.32969734
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3618226430
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3841951365
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3394540380
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.4013664330
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.359398960
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2843427886
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1907572767
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4034373497
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1683911065
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3523563305
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3007506085
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1021405953
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1452014707
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1749478788
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.65378504
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.1873135092
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2159142323
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2094277287
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.4107028244
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1626247149
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.2371999136
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3945640713
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.4247806430
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.289368939
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3574021449
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2907626659
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1997057840
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1778115203
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3563514162
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3563942092
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1018284373
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1070695430
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3753691287
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.115653047
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.287711433
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.4194043704
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.789661831
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1260560907
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.2225272892
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2982191952
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.89154338
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.254401580
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2422746013
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.909737136
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1869283452
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1780616888
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.1006216777
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3340040574
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3085462250
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.1383691629
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.1201147960
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2868853805
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.144015405
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1222705904
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3125319027
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.2406964243
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.582690416
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1658439943
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.398281198
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2509074870
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.149756417
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2151825882
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1475335888
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2898031751
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3555574978
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3048523086
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.4114168962
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4007774732
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.988065321
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.3394916312
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3225598125
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3440899148
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3265248111
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1111337075
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1893817777
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.3947312832
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.127636376
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2940931253
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1041771276
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2511588721
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1706881171
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.494964349
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.791812436
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1384545074
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.925938748
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3090864110
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3727068251
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1046978342
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3286935610
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.508107413
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1053121896
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.690779417
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2974846531
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4198873281
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.454251675
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.579870351
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.360667453
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.100816584
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.677719603
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.1539186255
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3092632957
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1083446932
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2219605691
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3529852537
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1884530525
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2630165427
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2353243289
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3464779309
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3942140781
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2220753310
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3312329362
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.2752593178
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.3157571715
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1560389638
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.920666441
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.2763759555
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2834742755
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.154591419
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2862357901
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.155485567
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2179521386
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2171210976
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2828350785
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1123282096
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.405566773
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.1435116714
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3681726543
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.2945755653
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2570863784
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4133243738
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3848647139
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/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_tx_rx.889024225
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/80.uart_fifo_reset.2403581569
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/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/81.uart_fifo_reset.819774437
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/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/89.uart_fifo_reset.3280047979
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/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_alert_test.800901347
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/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.2584311840
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/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3057181461
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/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/93.uart_fifo_reset.3660016733
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.3691911512
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/94.uart_fifo_reset.921164622
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.932707862
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2305794665
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.4030530723
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/96.uart_fifo_reset.3476706025
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.1884969811
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3907021500
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.761863488
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2971489314
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.552262251
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/99.uart_fifo_reset.2214758914
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.2768896786



Total test records in report: 1318
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2015846310 Sep 11 02:55:57 AM UTC 24 Sep 11 02:56:00 AM UTC 24 2739869853 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.4193545833 Sep 11 02:55:57 AM UTC 24 Sep 11 02:56:01 AM UTC 24 2522234564 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_rx_oversample.1559954236 Sep 11 02:55:57 AM UTC 24 Sep 11 02:56:02 AM UTC 24 2352461140 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_alert_test.2419037248 Sep 11 02:56:00 AM UTC 24 Sep 11 02:56:05 AM UTC 24 16673385 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_smoke.2334982187 Sep 11 02:55:56 AM UTC 24 Sep 11 02:56:05 AM UTC 24 103656962 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_sec_cm.1169502644 Sep 11 02:56:00 AM UTC 24 Sep 11 02:56:05 AM UTC 24 88681829 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_loopback.1067029679 Sep 11 02:55:59 AM UTC 24 Sep 11 02:56:07 AM UTC 24 6887435861 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_smoke.3606197345 Sep 11 02:56:00 AM UTC 24 Sep 11 02:56:08 AM UTC 24 549851642 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_alert_test.2315328042 Sep 11 02:56:06 AM UTC 24 Sep 11 02:56:08 AM UTC 24 13066454 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_sec_cm.720651374 Sep 11 02:56:06 AM UTC 24 Sep 11 02:56:08 AM UTC 24 60780337 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_smoke.3938491423 Sep 11 02:56:06 AM UTC 24 Sep 11 02:56:09 AM UTC 24 885330646 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2316014675 Sep 11 02:56:02 AM UTC 24 Sep 11 02:56:12 AM UTC 24 3884002147 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.2470378977 Sep 11 02:56:12 AM UTC 24 Sep 11 02:56:17 AM UTC 24 1442020632 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2403240609 Sep 11 02:56:02 AM UTC 24 Sep 11 02:56:22 AM UTC 24 139888122179 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.211426004 Sep 11 02:56:01 AM UTC 24 Sep 11 02:56:22 AM UTC 24 16945081012 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_intr.2804810282 Sep 11 02:56:02 AM UTC 24 Sep 11 02:56:23 AM UTC 24 17334779208 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_alert_test.208428886 Sep 11 02:56:23 AM UTC 24 Sep 11 02:56:24 AM UTC 24 12410475 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_sec_cm.56665986 Sep 11 02:56:23 AM UTC 24 Sep 11 02:56:25 AM UTC 24 37814485 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_loopback.3490769322 Sep 11 02:56:03 AM UTC 24 Sep 11 02:56:25 AM UTC 24 5974170212 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_noise_filter.1591849509 Sep 11 02:56:02 AM UTC 24 Sep 11 02:56:26 AM UTC 24 53691826064 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_loopback.1587208564 Sep 11 02:56:17 AM UTC 24 Sep 11 02:56:27 AM UTC 24 3421282467 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_tx_rx.2816969887 Sep 11 02:55:57 AM UTC 24 Sep 11 02:56:29 AM UTC 24 112748136965 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.2936968646 Sep 11 02:56:08 AM UTC 24 Sep 11 02:56:29 AM UTC 24 38438119155 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_smoke.1339652748 Sep 11 02:56:24 AM UTC 24 Sep 11 02:56:30 AM UTC 24 886074912 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_intr.3140277748 Sep 11 02:56:08 AM UTC 24 Sep 11 02:56:35 AM UTC 24 6630848613 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3901401240 Sep 11 02:56:02 AM UTC 24 Sep 11 02:56:35 AM UTC 24 3696120702 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_alert_test.2757203456 Sep 11 02:56:36 AM UTC 24 Sep 11 02:56:38 AM UTC 24 45755972 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_sec_cm.339826329 Sep 11 02:56:36 AM UTC 24 Sep 11 02:56:38 AM UTC 24 240751262 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2911735312 Sep 11 02:56:06 AM UTC 24 Sep 11 02:56:39 AM UTC 24 1736612828 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2674330076 Sep 11 02:56:27 AM UTC 24 Sep 11 02:56:39 AM UTC 24 7219933015 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1389694527 Sep 11 02:56:08 AM UTC 24 Sep 11 02:56:40 AM UTC 24 39573150679 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_smoke.3301848147 Sep 11 02:56:38 AM UTC 24 Sep 11 02:56:41 AM UTC 24 782510503 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.4018875206 Sep 11 02:56:03 AM UTC 24 Sep 11 02:56:41 AM UTC 24 12725595159 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_loopback.2915005502 Sep 11 02:56:28 AM UTC 24 Sep 11 02:56:43 AM UTC 24 11712209889 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.1228289958 Sep 11 02:56:43 AM UTC 24 Sep 11 02:56:47 AM UTC 24 673817613 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_perf.1661080796 Sep 11 02:55:59 AM UTC 24 Sep 11 02:56:47 AM UTC 24 2740262457 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_rx_oversample.1842583602 Sep 11 02:56:08 AM UTC 24 Sep 11 02:56:48 AM UTC 24 4292783088 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.3409806714 Sep 11 02:56:40 AM UTC 24 Sep 11 02:56:49 AM UTC 24 7523334521 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_noise_filter.1209687860 Sep 11 02:56:09 AM UTC 24 Sep 11 02:56:50 AM UTC 24 41819509273 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.2595788963 Sep 11 02:56:47 AM UTC 24 Sep 11 02:56:51 AM UTC 24 874219465 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_alert_test.3419490040 Sep 11 02:56:51 AM UTC 24 Sep 11 02:56:53 AM UTC 24 11972745 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_sec_cm.2480930889 Sep 11 02:56:51 AM UTC 24 Sep 11 02:56:54 AM UTC 24 58275470 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_smoke.72320154 Sep 11 02:56:51 AM UTC 24 Sep 11 02:56:55 AM UTC 24 512569253 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_rx_oversample.3587690860 Sep 11 02:56:41 AM UTC 24 Sep 11 02:56:59 AM UTC 24 6655553099 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1507805292 Sep 11 02:56:09 AM UTC 24 Sep 11 02:56:59 AM UTC 24 22368026005 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_tx_rx.1219223793 Sep 11 02:56:01 AM UTC 24 Sep 11 02:57:00 AM UTC 24 50642109557 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.1182719045 Sep 11 02:55:57 AM UTC 24 Sep 11 02:57:02 AM UTC 24 35842890289 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1188237552 Sep 11 02:56:22 AM UTC 24 Sep 11 02:57:02 AM UTC 24 3384852220 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.172325477 Sep 11 02:56:00 AM UTC 24 Sep 11 02:57:03 AM UTC 24 20362885557 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2878635417 Sep 11 02:56:40 AM UTC 24 Sep 11 02:57:05 AM UTC 24 9039946646 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_intr.1793556800 Sep 11 02:56:26 AM UTC 24 Sep 11 02:57:06 AM UTC 24 48686805177 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_fifo_reset.1489661707 Sep 11 02:56:25 AM UTC 24 Sep 11 02:57:08 AM UTC 24 53299416150 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_alert_test.3686897056 Sep 11 02:57:07 AM UTC 24 Sep 11 02:57:09 AM UTC 24 17287304 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_loopback.2541002576 Sep 11 02:57:01 AM UTC 24 Sep 11 02:57:09 AM UTC 24 6301237210 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_tx_rx.3816913803 Sep 11 02:56:07 AM UTC 24 Sep 11 02:57:11 AM UTC 24 124397834057 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_smoke.1162789938 Sep 11 02:57:09 AM UTC 24 Sep 11 02:57:13 AM UTC 24 645570605 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_loopback.3520923416 Sep 11 02:56:48 AM UTC 24 Sep 11 02:57:13 AM UTC 24 14382035235 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_fifo_reset.531887492 Sep 11 02:56:55 AM UTC 24 Sep 11 02:57:16 AM UTC 24 20361669947 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_noise_filter.2012552447 Sep 11 02:56:41 AM UTC 24 Sep 11 02:57:16 AM UTC 24 14028112152 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.4087702515 Sep 11 02:57:00 AM UTC 24 Sep 11 02:57:17 AM UTC 24 42120016447 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.296909277 Sep 11 02:56:31 AM UTC 24 Sep 11 02:57:17 AM UTC 24 2970004150 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_rx_oversample.3317167638 Sep 11 02:56:56 AM UTC 24 Sep 11 02:57:18 AM UTC 24 4298305713 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.30665158 Sep 11 02:56:49 AM UTC 24 Sep 11 02:57:19 AM UTC 24 20903487224 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.1913172242 Sep 11 02:57:05 AM UTC 24 Sep 11 02:57:19 AM UTC 24 2102514894 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_intr.4223973226 Sep 11 02:57:16 AM UTC 24 Sep 11 02:57:22 AM UTC 24 7230258711 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.3026216631 Sep 11 02:56:09 AM UTC 24 Sep 11 02:57:22 AM UTC 24 77934967114 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_rx_oversample.1574406859 Sep 11 02:56:25 AM UTC 24 Sep 11 02:57:22 AM UTC 24 6267099595 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.129587611 Sep 11 02:57:18 AM UTC 24 Sep 11 02:57:23 AM UTC 24 790807167 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_alert_test.115585412 Sep 11 02:57:22 AM UTC 24 Sep 11 02:57:24 AM UTC 24 10458515 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.609168208 Sep 11 02:57:01 AM UTC 24 Sep 11 02:57:25 AM UTC 24 6231322875 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_loopback.1576909082 Sep 11 02:57:20 AM UTC 24 Sep 11 02:57:25 AM UTC 24 3537447161 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_intr.996296121 Sep 11 02:56:57 AM UTC 24 Sep 11 02:57:25 AM UTC 24 33380679949 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_intr.81533557 Sep 11 02:56:41 AM UTC 24 Sep 11 02:57:26 AM UTC 24 54883285870 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_smoke.4235266500 Sep 11 02:57:23 AM UTC 24 Sep 11 02:57:29 AM UTC 24 6152902026 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_fifo_reset.4205754136 Sep 11 02:57:12 AM UTC 24 Sep 11 02:57:29 AM UTC 24 50444776921 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_rx_oversample.1286648104 Sep 11 02:57:14 AM UTC 24 Sep 11 02:57:30 AM UTC 24 4207951558 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_perf.3772752781 Sep 11 02:56:30 AM UTC 24 Sep 11 02:57:31 AM UTC 24 4568226077 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.4101580035 Sep 11 02:57:29 AM UTC 24 Sep 11 02:57:32 AM UTC 24 7323339856 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.1739937843 Sep 11 02:56:24 AM UTC 24 Sep 11 02:57:34 AM UTC 24 245071434855 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_tx_rx.2212823699 Sep 11 02:56:53 AM UTC 24 Sep 11 02:57:35 AM UTC 24 34586999839 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.2193709738 Sep 11 02:57:31 AM UTC 24 Sep 11 02:57:35 AM UTC 24 1987496172 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3443739775 Sep 11 02:56:49 AM UTC 24 Sep 11 02:57:41 AM UTC 24 3683029196 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.1835297230 Sep 11 02:57:20 AM UTC 24 Sep 11 02:57:41 AM UTC 24 1534814024 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_loopback.917949659 Sep 11 02:57:33 AM UTC 24 Sep 11 02:57:42 AM UTC 24 7048051432 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_alert_test.1743890700 Sep 11 02:57:42 AM UTC 24 Sep 11 02:57:43 AM UTC 24 43212437 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_rx_oversample.3452623973 Sep 11 02:57:27 AM UTC 24 Sep 11 02:57:46 AM UTC 24 4008955260 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_noise_filter.2013047515 Sep 11 02:55:57 AM UTC 24 Sep 11 02:57:47 AM UTC 24 52307871819 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.2715817063 Sep 11 02:56:27 AM UTC 24 Sep 11 02:57:48 AM UTC 24 35890829298 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_noise_filter.2313523999 Sep 11 02:56:26 AM UTC 24 Sep 11 02:57:49 AM UTC 24 34909104680 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.4124765424 Sep 11 02:57:12 AM UTC 24 Sep 11 02:57:50 AM UTC 24 39168985650 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_fifo_full.2841862343 Sep 11 02:55:57 AM UTC 24 Sep 11 02:57:51 AM UTC 24 237494782211 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_fifo_full.2002289045 Sep 11 02:57:12 AM UTC 24 Sep 11 02:57:52 AM UTC 24 54000249251 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_smoke.1095616041 Sep 11 02:57:42 AM UTC 24 Sep 11 02:57:53 AM UTC 24 5519966586 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.2935664684 Sep 11 02:57:01 AM UTC 24 Sep 11 02:57:54 AM UTC 24 29914987775 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_fifo_full.1125654372 Sep 11 02:57:25 AM UTC 24 Sep 11 02:57:55 AM UTC 24 18122478081 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_fifo_full.1544161151 Sep 11 02:56:54 AM UTC 24 Sep 11 02:57:57 AM UTC 24 70260625646 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2678158443 Sep 11 02:57:54 AM UTC 24 Sep 11 02:58:02 AM UTC 24 868096795 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.3184914103 Sep 11 02:57:52 AM UTC 24 Sep 11 02:58:06 AM UTC 24 35348937202 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2752595746 Sep 11 02:57:27 AM UTC 24 Sep 11 02:58:06 AM UTC 24 11745437707 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_loopback.3208903126 Sep 11 02:57:54 AM UTC 24 Sep 11 02:58:08 AM UTC 24 9969578225 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_noise_filter.3592404969 Sep 11 02:57:18 AM UTC 24 Sep 11 02:58:08 AM UTC 24 91985623465 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_alert_test.3195399472 Sep 11 02:58:08 AM UTC 24 Sep 11 02:58:10 AM UTC 24 56581313 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1270569153 Sep 11 02:57:50 AM UTC 24 Sep 11 02:58:10 AM UTC 24 3287458863 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_smoke.3297035505 Sep 11 02:58:08 AM UTC 24 Sep 11 02:58:10 AM UTC 24 277660468 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.4015964450 Sep 11 02:57:58 AM UTC 24 Sep 11 02:58:10 AM UTC 24 2616223594 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.875683812 Sep 11 02:57:31 AM UTC 24 Sep 11 02:58:13 AM UTC 24 196489105984 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_intr.1847580793 Sep 11 02:58:12 AM UTC 24 Sep 11 02:58:14 AM UTC 24 470644737 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_fifo_reset.4173113923 Sep 11 02:57:48 AM UTC 24 Sep 11 02:58:15 AM UTC 24 13849487725 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_tx_rx.3407993449 Sep 11 02:57:09 AM UTC 24 Sep 11 02:58:16 AM UTC 24 99439104071 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_fifo_full.2233714817 Sep 11 02:56:07 AM UTC 24 Sep 11 02:58:17 AM UTC 24 83810871320 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_loopback.2652545487 Sep 11 02:58:17 AM UTC 24 Sep 11 02:58:22 AM UTC 24 1543503292 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.1661127755 Sep 11 02:56:44 AM UTC 24 Sep 11 02:58:23 AM UTC 24 190411165852 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.475023965 Sep 11 02:58:15 AM UTC 24 Sep 11 02:58:23 AM UTC 24 1658411087 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2394128117 Sep 11 02:57:54 AM UTC 24 Sep 11 02:58:26 AM UTC 24 36425661776 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.574903667 Sep 11 02:57:18 AM UTC 24 Sep 11 02:58:27 AM UTC 24 49233655256 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_noise_filter.211268752 Sep 11 02:57:00 AM UTC 24 Sep 11 02:58:27 AM UTC 24 116422301856 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_alert_test.800901347 Sep 11 02:58:27 AM UTC 24 Sep 11 02:58:29 AM UTC 24 12319441 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.4276417168 Sep 11 02:57:18 AM UTC 24 Sep 11 02:58:32 AM UTC 24 33068181174 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.4125654854 Sep 11 02:58:16 AM UTC 24 Sep 11 02:58:32 AM UTC 24 7523676891 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2871121799 Sep 11 02:56:01 AM UTC 24 Sep 11 02:58:32 AM UTC 24 51584761515 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_smoke.2872385690 Sep 11 02:58:28 AM UTC 24 Sep 11 02:58:33 AM UTC 24 427474029 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.3404365616 Sep 11 02:58:35 AM UTC 24 Sep 11 02:58:42 AM UTC 24 1584138042 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_intr.592795894 Sep 11 02:58:33 AM UTC 24 Sep 11 02:58:42 AM UTC 24 15703864216 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1032248690 Sep 11 02:58:43 AM UTC 24 Sep 11 02:58:45 AM UTC 24 1824944831 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_tx_rx.1765023115 Sep 11 02:56:24 AM UTC 24 Sep 11 02:58:48 AM UTC 24 280118348634 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_rx_oversample.1202592042 Sep 11 02:58:12 AM UTC 24 Sep 11 02:58:48 AM UTC 24 4192770145 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_tx_rx.1882659120 Sep 11 02:58:28 AM UTC 24 Sep 11 02:58:50 AM UTC 24 38167226532 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_loopback.3614857944 Sep 11 02:58:47 AM UTC 24 Sep 11 02:58:55 AM UTC 24 1651285412 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_intr.424975029 Sep 11 02:55:57 AM UTC 24 Sep 11 02:58:57 AM UTC 24 75244665619 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.3307139412 Sep 11 02:57:25 AM UTC 24 Sep 11 02:58:59 AM UTC 24 103228548238 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_alert_test.3233917420 Sep 11 02:58:58 AM UTC 24 Sep 11 02:59:00 AM UTC 24 32090590 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_smoke.135992240 Sep 11 02:59:00 AM UTC 24 Sep 11 02:59:04 AM UTC 24 471202021 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3313833939 Sep 11 02:55:57 AM UTC 24 Sep 11 02:59:04 AM UTC 24 215664925113 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.2584311840 Sep 11 02:58:10 AM UTC 24 Sep 11 02:59:06 AM UTC 24 100796508524 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_fifo_reset.3396715704 Sep 11 02:58:12 AM UTC 24 Sep 11 02:59:07 AM UTC 24 91081964186 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_fifo_full.3677457179 Sep 11 02:58:10 AM UTC 24 Sep 11 02:59:10 AM UTC 24 77458936401 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_rx_oversample.2364513479 Sep 11 02:58:33 AM UTC 24 Sep 11 02:59:11 AM UTC 24 6359489949 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3250923698 Sep 11 02:58:15 AM UTC 24 Sep 11 02:59:13 AM UTC 24 103004486704 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_noise_filter.2483837590 Sep 11 02:58:14 AM UTC 24 Sep 11 02:59:15 AM UTC 24 27842551334 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.2778282063 Sep 11 02:56:18 AM UTC 24 Sep 11 02:59:18 AM UTC 24 82360593925 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_fifo_full.1423250387 Sep 11 02:56:24 AM UTC 24 Sep 11 02:59:21 AM UTC 24 129611025523 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_tx_rx.3527168929 Sep 11 02:56:39 AM UTC 24 Sep 11 02:59:24 AM UTC 24 83833412612 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_intr.2231841740 Sep 11 02:59:11 AM UTC 24 Sep 11 02:59:26 AM UTC 24 41280439685 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.829793041 Sep 11 02:58:51 AM UTC 24 Sep 11 02:59:29 AM UTC 24 7650636515 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_stress_all.4075383529 Sep 11 02:58:04 AM UTC 24 Sep 11 02:59:29 AM UTC 24 66816212264 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.1810577690 Sep 11 02:58:24 AM UTC 24 Sep 11 02:59:33 AM UTC 24 8247177003 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_stress_all.2545513345 Sep 11 02:56:50 AM UTC 24 Sep 11 02:59:35 AM UTC 24 88736219087 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_alert_test.701415951 Sep 11 02:59:33 AM UTC 24 Sep 11 02:59:35 AM UTC 24 91575772 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_rx_oversample.4139399770 Sep 11 02:59:09 AM UTC 24 Sep 11 02:59:36 AM UTC 24 4424969548 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_tx_rx.3657594424 Sep 11 02:58:10 AM UTC 24 Sep 11 02:59:36 AM UTC 24 75704588885 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_full.3825874130 Sep 11 02:56:01 AM UTC 24 Sep 11 02:59:37 AM UTC 24 224354504092 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_smoke.784669663 Sep 11 02:59:35 AM UTC 24 Sep 11 02:59:38 AM UTC 24 279598924 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_loopback.2495116369 Sep 11 02:59:22 AM UTC 24 Sep 11 02:59:40 AM UTC 24 6681776366 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_intr.578228614 Sep 11 02:57:27 AM UTC 24 Sep 11 02:59:42 AM UTC 24 140215962635 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.622889523 Sep 11 02:59:14 AM UTC 24 Sep 11 02:59:44 AM UTC 24 39787783729 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_fifo_full.2572856943 Sep 11 02:58:30 AM UTC 24 Sep 11 02:59:45 AM UTC 24 27784099066 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_noise_filter.2411960261 Sep 11 02:58:33 AM UTC 24 Sep 11 02:59:46 AM UTC 24 112856067693 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.3250743930 Sep 11 02:59:37 AM UTC 24 Sep 11 02:59:47 AM UTC 24 34322761725 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_tx_rx.1835853089 Sep 11 02:59:37 AM UTC 24 Sep 11 02:59:47 AM UTC 24 4814111721 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.46336157 Sep 11 02:59:19 AM UTC 24 Sep 11 02:59:49 AM UTC 24 6286280468 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.2466354615 Sep 11 02:59:47 AM UTC 24 Sep 11 02:59:50 AM UTC 24 962743051 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_tx_rx.641790122 Sep 11 02:57:23 AM UTC 24 Sep 11 02:59:51 AM UTC 24 51710586257 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.2490223202 Sep 11 02:59:45 AM UTC 24 Sep 11 02:59:53 AM UTC 24 3026888392 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_alert_test.4233880319 Sep 11 02:59:54 AM UTC 24 Sep 11 02:59:55 AM UTC 24 31577261 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_loopback.671198096 Sep 11 02:59:47 AM UTC 24 Sep 11 02:59:56 AM UTC 24 5370464802 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_smoke.4277277996 Sep 11 02:59:57 AM UTC 24 Sep 11 02:59:59 AM UTC 24 308611130 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_perf.2197312319 Sep 11 02:57:56 AM UTC 24 Sep 11 03:00:03 AM UTC 24 12283765224 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.76193385 Sep 11 02:57:35 AM UTC 24 Sep 11 03:00:06 AM UTC 24 12771656172 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_fifo_full.2265540660 Sep 11 02:59:37 AM UTC 24 Sep 11 03:00:08 AM UTC 24 38736049568 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_fifo_full.4180747574 Sep 11 02:56:39 AM UTC 24 Sep 11 03:00:10 AM UTC 24 106937902942 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2580827199 Sep 11 02:55:57 AM UTC 24 Sep 11 03:00:10 AM UTC 24 46638075671 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_perf.2143411172 Sep 11 02:56:48 AM UTC 24 Sep 11 03:00:13 AM UTC 24 13421109611 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_tx_rx.806893129 Sep 11 02:59:00 AM UTC 24 Sep 11 03:00:17 AM UTC 24 48822812321 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.3172334036 Sep 11 02:56:27 AM UTC 24 Sep 11 03:00:22 AM UTC 24 128751257091 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3019616249 Sep 11 03:00:09 AM UTC 24 Sep 11 03:00:23 AM UTC 24 4477410069 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_rx_oversample.1195318359 Sep 11 02:59:39 AM UTC 24 Sep 11 03:00:24 AM UTC 24 7202452960 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_intr.726333788 Sep 11 03:00:10 AM UTC 24 Sep 11 03:00:25 AM UTC 24 4198843202 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.2248764142 Sep 11 03:00:23 AM UTC 24 Sep 11 03:00:26 AM UTC 24 967364782 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_stress_all.2352246946 Sep 11 02:57:22 AM UTC 24 Sep 11 03:00:27 AM UTC 24 187969543959 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_loopback.745262901 Sep 11 03:00:23 AM UTC 24 Sep 11 03:00:28 AM UTC 24 1036308122 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_tx_rx.3132313469 Sep 11 02:59:58 AM UTC 24 Sep 11 03:00:30 AM UTC 24 10539584248 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_alert_test.970652873 Sep 11 03:00:29 AM UTC 24 Sep 11 03:00:31 AM UTC 24 76606320 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_fifo_reset.3998343853 Sep 11 03:00:07 AM UTC 24 Sep 11 03:00:34 AM UTC 24 31801629931 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2710930375 Sep 11 03:00:06 AM UTC 24 Sep 11 03:00:34 AM UTC 24 9432601755 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_smoke.3750628351 Sep 11 03:00:31 AM UTC 24 Sep 11 03:00:35 AM UTC 24 313218919 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_fifo_reset.1195666791 Sep 11 02:58:32 AM UTC 24 Sep 11 03:00:36 AM UTC 24 52553348470 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_stress_all.821746638 Sep 11 02:56:00 AM UTC 24 Sep 11 03:00:37 AM UTC 24 350474084257 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.2513177679 Sep 11 02:59:51 AM UTC 24 Sep 11 03:00:38 AM UTC 24 2444482321 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1264321618 Sep 11 02:59:29 AM UTC 24 Sep 11 03:00:45 AM UTC 24 4597426860 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.2294750181 Sep 11 02:56:30 AM UTC 24 Sep 11 03:00:45 AM UTC 24 189202237735 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_rx_oversample.1429571072 Sep 11 03:00:35 AM UTC 24 Sep 11 03:00:55 AM UTC 24 2969425154 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.3218060162 Sep 11 02:59:16 AM UTC 24 Sep 11 03:00:56 AM UTC 24 146946138306 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_loopback.2562024698 Sep 11 03:00:56 AM UTC 24 Sep 11 03:00:59 AM UTC 24 7651946691 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2531132550 Sep 11 03:00:17 AM UTC 24 Sep 11 03:01:00 AM UTC 24 18185382921 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_noise_filter.3739741474 Sep 11 02:57:52 AM UTC 24 Sep 11 03:01:03 AM UTC 24 145939737224 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_fifo_reset.1147398014 Sep 11 03:00:35 AM UTC 24 Sep 11 03:01:04 AM UTC 24 49148255674 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_alert_test.4007965386 Sep 11 03:01:04 AM UTC 24 Sep 11 03:01:06 AM UTC 24 31850189 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_noise_filter.4125099443 Sep 11 03:00:11 AM UTC 24 Sep 11 03:01:07 AM UTC 24 17429238128 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.923687048 Sep 11 03:00:47 AM UTC 24 Sep 11 03:01:07 AM UTC 24 6988785710 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_smoke.981064552 Sep 11 03:01:07 AM UTC 24 Sep 11 03:01:11 AM UTC 24 447458611 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.2914131613 Sep 11 03:00:34 AM UTC 24 Sep 11 03:01:14 AM UTC 24 43829535686 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_noise_filter.3265282957 Sep 11 02:59:12 AM UTC 24 Sep 11 03:01:16 AM UTC 24 216822998874 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.3915759341 Sep 11 03:00:46 AM UTC 24 Sep 11 03:01:17 AM UTC 24 41568115452 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_fifo_full.4161615019 Sep 11 03:00:33 AM UTC 24 Sep 11 03:01:17 AM UTC 24 61440127666 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_stress_all.1162157750 Sep 11 02:56:06 AM UTC 24 Sep 11 03:01:17 AM UTC 24 291956516942 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.2060954910 Sep 11 03:00:39 AM UTC 24 Sep 11 03:01:19 AM UTC 24 40692661674 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_perf.3039523516 Sep 11 02:56:03 AM UTC 24 Sep 11 03:01:23 AM UTC 24 4218385768 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3684847364 Sep 11 03:00:28 AM UTC 24 Sep 11 03:01:24 AM UTC 24 12859363680 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.1901531618 Sep 11 02:59:46 AM UTC 24 Sep 11 03:01:27 AM UTC 24 28388102223 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_loopback.2431769028 Sep 11 03:01:25 AM UTC 24 Sep 11 03:01:27 AM UTC 24 31523820 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.1379335890 Sep 11 03:01:01 AM UTC 24 Sep 11 03:01:29 AM UTC 24 3091820927 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3538872846 Sep 11 02:57:57 AM UTC 24 Sep 11 03:01:31 AM UTC 24 57268449320 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_perf.1047738221 Sep 11 02:59:25 AM UTC 24 Sep 11 03:01:33 AM UTC 24 10798966862 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_alert_test.2057611672 Sep 11 03:01:33 AM UTC 24 Sep 11 03:01:35 AM UTC 24 14140585 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_intr.1098035188 Sep 11 02:59:41 AM UTC 24 Sep 11 03:01:40 AM UTC 24 46784526260 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_smoke.412032868 Sep 11 03:01:37 AM UTC 24 Sep 11 03:01:43 AM UTC 24 889232552 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.846510331 Sep 11 02:56:55 AM UTC 24 Sep 11 03:01:44 AM UTC 24 121085489883 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_noise_filter.2820880961 Sep 11 03:01:18 AM UTC 24 Sep 11 03:01:45 AM UTC 24 160626402680 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.2518508241 Sep 11 03:01:20 AM UTC 24 Sep 11 03:01:47 AM UTC 24 61637945520 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_intr.409412343 Sep 11 03:01:18 AM UTC 24 Sep 11 03:01:49 AM UTC 24 35462009547 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.538157886 Sep 11 03:00:14 AM UTC 24 Sep 11 03:01:49 AM UTC 24 30282197610 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.718296749 Sep 11 03:01:29 AM UTC 24 Sep 11 03:01:52 AM UTC 24 2129897051 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.2973644833 Sep 11 03:01:24 AM UTC 24 Sep 11 03:01:53 AM UTC 24 13245888748 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_perf.4239056348 Sep 11 03:00:25 AM UTC 24 Sep 11 03:01:54 AM UTC 24 22396487863 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_stress_all.1149655218 Sep 11 02:56:23 AM UTC 24 Sep 11 03:01:54 AM UTC 24 190538806298 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_rx_oversample.3406616683 Sep 11 03:01:48 AM UTC 24 Sep 11 03:01:55 AM UTC 24 5904432232 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_tx_rx.3324563028 Sep 11 03:00:32 AM UTC 24 Sep 11 03:01:55 AM UTC 24 54802406259 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.1651283840 Sep 11 03:01:52 AM UTC 24 Sep 11 03:02:02 AM UTC 24 4290032049 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_fifo_full.495023237 Sep 11 03:00:00 AM UTC 24 Sep 11 03:02:04 AM UTC 24 173687111418 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_tx_rx.3717713515 Sep 11 03:01:08 AM UTC 24 Sep 11 03:02:06 AM UTC 24 59164031179 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_noise_filter.2148751649 Sep 11 03:00:37 AM UTC 24 Sep 11 03:02:06 AM UTC 24 72079938954 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_alert_test.3026934783 Sep 11 03:02:07 AM UTC 24 Sep 11 03:02:09 AM UTC 24 30596130 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_tx_rx.2906164532 Sep 11 03:01:41 AM UTC 24 Sep 11 03:02:09 AM UTC 24 64193341283 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_loopback.1332380028 Sep 11 03:01:54 AM UTC 24 Sep 11 03:02:10 AM UTC 24 10330747311 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_smoke.135130065 Sep 11 03:02:07 AM UTC 24 Sep 11 03:02:10 AM UTC 24 448578962 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.3428012972 Sep 11 03:01:54 AM UTC 24 Sep 11 03:02:11 AM UTC 24 6924998554 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.1589471779 Sep 11 02:58:43 AM UTC 24 Sep 11 03:02:12 AM UTC 24 95982169797 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.113871231 Sep 11 02:57:20 AM UTC 24 Sep 11 03:02:14 AM UTC 24 61502025765 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_fifo_reset.2738733605 Sep 11 02:59:07 AM UTC 24 Sep 11 03:02:20 AM UTC 24 149150602145 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3027535564 Sep 11 03:01:18 AM UTC 24 Sep 11 03:02:24 AM UTC 24 6306447243 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_stress_all.1368692866 Sep 11 02:56:36 AM UTC 24 Sep 11 03:02:27 AM UTC 24 153020075874 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_intr.4032158210 Sep 11 03:02:13 AM UTC 24 Sep 11 03:02:28 AM UTC 24 17507400044 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_noise_filter.981326138 Sep 11 02:59:43 AM UTC 24 Sep 11 03:02:30 AM UTC 24 162463523532 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_perf.2204130238 Sep 11 03:01:28 AM UTC 24 Sep 11 03:02:31 AM UTC 24 4466687530 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.2738403782 Sep 11 03:02:28 AM UTC 24 Sep 11 03:02:31 AM UTC 24 1188835603 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_noise_filter.912215811 Sep 11 02:57:27 AM UTC 24 Sep 11 03:02:32 AM UTC 24 108654614297 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_fifo_reset.3300626836 Sep 11 03:01:46 AM UTC 24 Sep 11 03:02:32 AM UTC 24 23719260846 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_stress_all.3372974048 Sep 11 03:01:03 AM UTC 24 Sep 11 03:02:34 AM UTC 24 138121440952 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_alert_test.2268796562 Sep 11 03:02:33 AM UTC 24 Sep 11 03:02:35 AM UTC 24 11973397 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_loopback.3731301325 Sep 11 03:02:30 AM UTC 24 Sep 11 03:02:36 AM UTC 24 1063021603 ps
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