Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1989	1			T3	4		T7	9		T24	6
auto[BaudRate115200]	1569	1			T1	1		T7	3		T8	1
auto[BaudRate230400]	1594	1			T7	3		T15	1		T11	3
auto[BaudRate128Kbps]	1515	1			T7	18		T14	2		T15	1
auto[BaudRate256Kbps]	1696	1			T2	2		T7	9		T11	5
auto[BaudRate1Mbps]	1440	1			T1	1		T5	1		T7	6
auto[BaudRate1p5Mbps]	1053	1			T5	1		T7	3		T12	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1138	1			T13	2		T44	10		T101	5
freqs[25]	1278	1			T1	2		T3	4		T16	2
freqs[48]	480	1			T23	2		T43	6		T45	2
freqs[50]	602	1			T7	51		T42	5		T319	2
freqs[100]	997	1			T22	9		T19	10		T41	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	174	1			T44	2		T101	1		T20	1
auto[BaudRate9600]	freqs[25]	219	1			T3	4		T379	12		T109	3
auto[BaudRate9600]	freqs[48]	73	1			T23	1		T43	1		T47	1
auto[BaudRate9600]	freqs[50]	80	1			T7	9		T319	2		T66	6
auto[BaudRate9600]	freqs[100]	241	1			T22	9		T26	10		T32	3
auto[BaudRate115200]	freqs[24]	167	1			T13	2		T44	1		T101	1
auto[BaudRate115200]	freqs[25]	185	1			T1	1		T16	1		T87	1
auto[BaudRate115200]	freqs[48]	66	1			T23	1		T43	1		T47	1
auto[BaudRate115200]	freqs[50]	82	1			T7	3		T66	8		T266	1
auto[BaudRate115200]	freqs[100]	132	1			T32	2		T279	1		T273	3
auto[BaudRate230400]	freqs[24]	178	1			T20	3		T380	3		T381	3
auto[BaudRate230400]	freqs[25]	174	1			T374	1		T87	1		T109	2
auto[BaudRate230400]	freqs[48]	57	1			T47	3		T272	1		T104	2
auto[BaudRate230400]	freqs[50]	76	1			T7	3		T42	1		T66	3
auto[BaudRate230400]	freqs[100]	131	1			T19	3		T32	2		T279	5
auto[BaudRate128Kbps]	freqs[24]	182	1			T44	2		T101	1		T20	5
auto[BaudRate128Kbps]	freqs[25]	168	1			T109	1		T265	1		T263	1
auto[BaudRate128Kbps]	freqs[48]	63	1			T43	2		T45	1		T47	3
auto[BaudRate128Kbps]	freqs[50]	96	1			T7	18		T42	1		T66	3
auto[BaudRate128Kbps]	freqs[100]	118	1			T19	2		T279	1		T273	2
auto[BaudRate256Kbps]	freqs[24]	158	1			T44	2		T20	1		T381	3
auto[BaudRate256Kbps]	freqs[25]	194	1			T87	1		T109	4		T265	1
auto[BaudRate256Kbps]	freqs[48]	75	1			T43	1		T47	1		T104	1
auto[BaudRate256Kbps]	freqs[50]	93	1			T7	9		T66	23		T355	2
auto[BaudRate256Kbps]	freqs[100]	115	1			T19	1		T103	1		T32	2
auto[BaudRate1Mbps]	freqs[24]	182	1			T44	2		T101	2		T20	1
auto[BaudRate1Mbps]	freqs[25]	229	1			T1	1		T16	1		T371	2
auto[BaudRate1Mbps]	freqs[48]	69	1			T43	1		T104	1		T382	3
auto[BaudRate1Mbps]	freqs[50]	81	1			T7	6		T42	2		T66	9
auto[BaudRate1Mbps]	freqs[100]	128	1			T19	2		T41	1		T103	3
auto[BaudRate1p5Mbps]	freqs[25]	109	1			T371	3		T87	2		T109	1
auto[BaudRate1p5Mbps]	freqs[48]	77	1			T45	1		T47	1		T104	2
auto[BaudRate1p5Mbps]	freqs[50]	94	1			T7	3		T42	1		T66	7
auto[BaudRate1p5Mbps]	freqs[100]	132	1			T19	2		T41	1		T103	6

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded