Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	20447473	1			T3	1		T7	6		T11	20
all_levels[1]	137900	1			T11	4		T12	2		T21	25
all_levels[2]	2227	1			T21	3		T17	6		T101	3
all_levels[3]	1031	1			T17	2		T101	2		T67	1
all_levels[4]	655	1			T17	2		T101	1		T47	2
all_levels[5]	530	1			T17	3		T37	3		T47	2
all_levels[6]	387	1			T17	1		T67	2		T102	2
all_levels[7]	294	1			T17	2		T102	1		T87	1
all_levels[8]	240	1			T17	1		T20	2		T103	3
all_levels[9]	198	1			T17	2		T20	2		T104	2
all_levels[10]	187	1			T12	1		T17	3		T44	1
all_levels[11]	141	1			T12	1		T17	1		T43	1
all_levels[12]	147	1			T17	1		T102	1		T84	1
all_levels[13]	135	1			T105	1		T27	1		T102	2
all_levels[14]	119	1			T105	1		T106	1		T107	2
all_levels[15]	106	1			T103	3		T108	1		T106	1
all_levels[16]	89	1			T103	1		T87	1		T84	1
all_levels[17]	81	1			T109	1		T110	1		T111	1
all_levels[18]	75	1			T84	1		T112	3		T113	1
all_levels[19]	62	1			T114	2		T90	1		T110	3
all_levels[20]	54	1			T67	3		T115	1		T87	1
all_levels[21]	72	1			T43	1		T105	2		T116	2
all_levels[22]	46	1			T117	1		T111	1		T118	1
all_levels[23]	49	1			T84	1		T117	1		T119	1
all_levels[24]	50	1			T117	2		T120	1		T121	1
all_levels[25]	47	1			T67	1		T105	1		T116	1
all_levels[26]	30	1			T112	1		T111	1		T121	2
all_levels[27]	31	1			T86	1		T110	1		T122	1
all_levels[28]	32	1			T67	2		T87	1		T110	2
all_levels[29]	42	1			T123	1		T122	1		T124	1
all_levels[30]	34	1			T11	1		T87	1		T110	1
all_levels[31]	32	1			T110	1		T112	3		T125	1
all_levels[32]	22	1			T44	1		T126	1		T127	1
all_levels[33]	22	1			T12	1		T107	1		T118	1
all_levels[34]	26	1			T111	1		T128	1		T129	2
all_levels[35]	20	1			T130	1		T131	1		T132	1
all_levels[36]	17	1			T133	1		T124	1		T134	1
all_levels[37]	23	1			T124	1		T119	1		T135	2
all_levels[38]	48	1			T103	1		T136	1		T137	2
all_levels[39]	13	1			T43	1		T87	1		T111	1
all_levels[40]	14	1			T112	1		T124	1		T138	1
all_levels[41]	11	1			T119	1		T139	2		T140	2
all_levels[42]	14	1			T141	1		T136	1		T96	2
all_levels[43]	18	1			T91	1		T142	1		T143	1
all_levels[44]	19	1			T103	2		T87	1		T118	1
all_levels[45]	17	1			T123	1		T144	1		T136	1
all_levels[46]	6	1			T145	1		T146	1		T147	1
all_levels[47]	16	1			T94	1		T148	2		T149	1
all_levels[48]	15	1			T150	1		T94	1		T151	1
all_levels[49]	18	1			T12	1		T105	1		T152	1
all_levels[50]	8	1			T152	1		T144	1		T153	1
all_levels[51]	12	1			T141	1		T152	1		T142	3
all_levels[52]	19	1			T12	1		T87	1		T116	1
all_levels[53]	9	1			T154	1		T155	1		T156	1
all_levels[54]	11	1			T123	1		T111	1		T94	1
all_levels[55]	3	1			T157	1		T158	1		T159	1
all_levels[56]	11	1			T111	1		T160	1		T161	1
all_levels[57]	13	1			T111	1		T162	1		T163	2
all_levels[58]	5	1			T164	1		T165	2		T166	1
all_levels[59]	3	1			T164	2		T167	1		-	-
all_levels[60]	8	1			T168	1		T169	1		T170	1
all_levels[61]	9	1			T87	1		T113	1		T157	1
all_levels[62]	8	1			T110	1		T113	1		T171	1
all_levels[63]	10	1			T92	1		T172	1		T173	3
all_levels[64]	88	1			T11	1		T86	1		T168	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20589153

1

T11

26

T12

37

T13

1196

auto[1]

3999

1

T3

1

T7

6

T13

22

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[27]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	20443905	1			T11	20		T12	30		T13	1196
all_levels[0]	auto[1]	3568	1			T3	1		T7	6		T13	22
all_levels[1]	auto[0]	137825	1			T11	4		T12	2		T21	25
all_levels[1]	auto[1]	75	1			T126	1		T142	1		T174	1
all_levels[2]	auto[0]	2201	1			T21	3		T17	6		T101	3
all_levels[2]	auto[1]	26	1			T175	2		T176	1		T177	2
all_levels[3]	auto[0]	1027	1			T17	2		T101	2		T67	1
all_levels[3]	auto[1]	4	1			T178	1		T179	1		T180	1
all_levels[4]	auto[0]	629	1			T17	2		T101	1		T47	2
all_levels[4]	auto[1]	26	1			T130	1		T126	1		T181	3
all_levels[5]	auto[0]	512	1			T17	3		T37	1		T47	2
all_levels[5]	auto[1]	18	1			T37	2		T182	1		T183	1
all_levels[6]	auto[0]	367	1			T17	1		T67	2		T102	2
all_levels[6]	auto[1]	20	1			T184	1		T185	2		T140	1
all_levels[7]	auto[0]	284	1			T17	2		T102	1		T87	1
all_levels[7]	auto[1]	10	1			T186	2		T187	1		T188	1
all_levels[8]	auto[0]	229	1			T17	1		T20	2		T103	2
all_levels[8]	auto[1]	11	1			T103	1		T119	1		T148	3
all_levels[9]	auto[0]	191	1			T17	2		T20	2		T104	2
all_levels[9]	auto[1]	7	1			T189	1		T190	1		T191	1
all_levels[10]	auto[0]	172	1			T12	1		T17	3		T44	1
all_levels[10]	auto[1]	15	1			T192	1		T193	2		T194	1
all_levels[11]	auto[0]	137	1			T12	1		T17	1		T43	1
all_levels[11]	auto[1]	4	1			T129	1		T195	1		T196	1
all_levels[12]	auto[0]	138	1			T17	1		T102	1		T84	1
all_levels[12]	auto[1]	9	1			T197	1		T198	1		T199	1
all_levels[13]	auto[0]	127	1			T105	1		T27	1		T102	2
all_levels[13]	auto[1]	8	1			T200	2		T201	1		T202	2
all_levels[14]	auto[0]	108	1			T105	1		T106	1		T107	1
all_levels[14]	auto[1]	11	1			T107	1		T199	3		T203	2
all_levels[15]	auto[0]	101	1			T103	1		T108	1		T106	1
all_levels[15]	auto[1]	5	1			T103	2		T121	1		T204	1
all_levels[16]	auto[0]	84	1			T103	1		T87	1		T84	1
all_levels[16]	auto[1]	5	1			T205	2		T206	1		T207	2
all_levels[17]	auto[0]	76	1			T109	1		T110	1		T111	1
all_levels[17]	auto[1]	5	1			T173	1		T208	1		T209	1
all_levels[18]	auto[0]	69	1			T84	1		T112	3		T113	1
all_levels[18]	auto[1]	6	1			T94	1		T210	1		T211	2
all_levels[19]	auto[0]	56	1			T114	2		T90	1		T110	3
all_levels[19]	auto[1]	6	1			T132	3		T181	1		T212	1
all_levels[20]	auto[0]	52	1			T67	3		T115	1		T87	1
all_levels[20]	auto[1]	2	1			T194	1		T213	1		-	-
all_levels[21]	auto[0]	65	1			T43	1		T105	2		T116	2
all_levels[21]	auto[1]	7	1			T214	1		T112	1		T187	1
all_levels[22]	auto[0]	40	1			T117	1		T111	1		T118	1
all_levels[22]	auto[1]	6	1			T215	1		T216	1		T217	1
all_levels[23]	auto[0]	43	1			T84	1		T117	1		T119	1
all_levels[23]	auto[1]	6	1			T218	1		T219	1		T220	1
all_levels[24]	auto[0]	42	1			T117	2		T120	1		T121	1
all_levels[24]	auto[1]	8	1			T94	1		T221	1		T191	1
all_levels[25]	auto[0]	38	1			T67	1		T105	1		T116	1
all_levels[25]	auto[1]	9	1			T222	1		T223	1		T224	1
all_levels[26]	auto[0]	27	1			T112	1		T111	1		T121	1
all_levels[26]	auto[1]	3	1			T121	1		T225	1		T226	1
all_levels[27]	auto[0]	31	1			T86	1		T110	1		T122	1
all_levels[28]	auto[0]	31	1			T67	2		T87	1		T110	2
all_levels[28]	auto[1]	1	1			T227	1		-	-		-	-
all_levels[29]	auto[0]	38	1			T123	1		T122	1		T124	1
all_levels[29]	auto[1]	4	1			T228	4		-	-		-	-
all_levels[30]	auto[0]	31	1			T11	1		T87	1		T110	1
all_levels[30]	auto[1]	3	1			T229	1		T230	2		-	-
all_levels[31]	auto[0]	27	1			T110	1		T112	1		T125	1
all_levels[31]	auto[1]	5	1			T112	2		T231	1		T179	1
all_levels[32]	auto[0]	21	1			T44	1		T126	1		T127	1
all_levels[32]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[33]	auto[0]	18	1			T12	1		T107	1		T118	1
all_levels[33]	auto[1]	4	1			T198	4		-	-		-	-
all_levels[34]	auto[0]	21	1			T111	1		T128	1		T129	2
all_levels[34]	auto[1]	5	1			T132	3		T233	2		-	-
all_levels[35]	auto[0]	18	1			T130	1		T131	1		T132	1
all_levels[35]	auto[1]	2	1			T198	1		T234	1		-	-
all_levels[36]	auto[0]	13	1			T133	1		T124	1		T134	1
all_levels[36]	auto[1]	4	1			T235	1		T236	1		T237	2
all_levels[37]	auto[0]	18	1			T124	1		T119	1		T135	1
all_levels[37]	auto[1]	5	1			T135	1		T142	2		T215	2
all_levels[38]	auto[0]	21	1			T103	1		T136	1		T137	2
all_levels[38]	auto[1]	27	1			T165	26		T238	1		-	-
all_levels[39]	auto[0]	10	1			T43	1		T87	1		T111	1
all_levels[39]	auto[1]	3	1			T239	3		-	-		-	-
all_levels[40]	auto[0]	14	1			T112	1		T124	1		T138	1
all_levels[41]	auto[0]	10	1			T119	1		T139	2		T140	2
all_levels[41]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[42]	auto[0]	14	1			T141	1		T136	1		T96	2
all_levels[43]	auto[0]	15	1			T91	1		T142	1		T143	1
all_levels[43]	auto[1]	3	1			T241	1		T242	2		-	-
all_levels[44]	auto[0]	16	1			T103	1		T87	1		T118	1
all_levels[44]	auto[1]	3	1			T103	1		T223	1		T243	1
all_levels[45]	auto[0]	17	1			T123	1		T144	1		T136	1
all_levels[46]	auto[0]	5	1			T145	1		T146	1		T147	1
all_levels[46]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[47]	auto[0]	15	1			T94	1		T148	1		T149	1
all_levels[47]	auto[1]	1	1			T148	1		-	-		-	-
all_levels[48]	auto[0]	13	1			T150	1		T94	1		T151	1
all_levels[48]	auto[1]	2	1			T245	2		-	-		-	-
all_levels[49]	auto[0]	13	1			T12	1		T105	1		T152	1
all_levels[49]	auto[1]	5	1			T121	1		T246	2		T247	2
all_levels[50]	auto[0]	8	1			T152	1		T144	1		T153	1
all_levels[51]	auto[0]	9	1			T141	1		T152	1		T142	1
all_levels[51]	auto[1]	3	1			T142	2		T188	1		-	-
all_levels[52]	auto[0]	17	1			T12	1		T87	1		T116	1
all_levels[52]	auto[1]	2	1			T212	1		T217	1		-	-
all_levels[53]	auto[0]	6	1			T154	1		T155	1		T156	1
all_levels[53]	auto[1]	3	1			T179	2		T248	1		-	-
all_levels[54]	auto[0]	10	1			T123	1		T111	1		T94	1
all_levels[54]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[55]	auto[0]	3	1			T157	1		T158	1		T159	1
all_levels[56]	auto[0]	8	1			T111	1		T160	1		T161	1
all_levels[56]	auto[1]	3	1			T250	3		-	-		-	-
all_levels[57]	auto[0]	10	1			T111	1		T162	1		T163	2
all_levels[57]	auto[1]	3	1			T251	1		T209	2		-	-
all_levels[58]	auto[0]	4	1			T164	1		T165	1		T166	1
all_levels[58]	auto[1]	1	1			T165	1		-	-		-	-
all_levels[59]	auto[0]	3	1			T164	2		T167	1		-	-
all_levels[60]	auto[0]	7	1			T168	1		T169	1		T170	1
all_levels[60]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[61]	auto[0]	9	1			T87	1		T113	1		T157	1
all_levels[62]	auto[0]	8	1			T110	1		T113	1		T171	1
all_levels[63]	auto[0]	7	1			T92	1		T172	1		T173	1
all_levels[63]	auto[1]	3	1			T173	2		T211	1		-	-
all_levels[64]	auto[0]	69	1			T11	1		T86	1		T168	1
all_levels[64]	auto[1]	19	1			T119	1		T184	1		T235	3